llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
Author: Fabian Mora (fabianmcg)
Changes
This patch adds the `gather`, `masked_load`, `masked_store`, and `scatter`
operations to the `ptr` dialect. It also implements translation from these
operations to LLVM intrinsics:
- ptr.gather -> llvm.
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/149064
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https://github.com/llvm/llvm-project/pull/156362
>From fe7aa772ca06338ec5a42b2a3fe9e78a22559149 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From 8961a0c7eb2c5fc7f93ad2d79e8dd2b6b3eab03a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
This is in
llvmbot wrote:
@hubert-reinterpretcast What do you think about merging this PR to the release
branch?
https://github.com/llvm/llvm-project/pull/156504
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https://github.com/llvm/llvm-project/pull/156502
Backport b8456e2a9698aa927d7b3f9c38213f3219aa0498
Requested by: @amy-kwan
>From 31292e1a3428feffb46e5a853699b1c587bb04e7 Mon Sep 17 00:00:00 2001
From: David Tenty
Date: Wed, 27 Aug 2025 18:28:26 -0400
Subject
@@ -250,6 +286,9 @@ struct MachineSMEABI : public MachineFunctionPass {
SmallVector BundleStates;
gbossu wrote:
We are starting to accumulate a lot of state, which makes the code harder to
follow as it allows any member function to modify it instead of havi
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/155866
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https://github.com/llvm/llvm-project/pull/155595
>From a6e2e0d83c2724f04313372df0deda5d1f889ed6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 19:39:38 +0900
Subject: [PATCH 1/2] AMDGPU: Fix DPP combiner using isOperandLegal on
incomplete
@@ -56,6 +96,58 @@ def Ptr_FromPtrOp : Pointer_Op<"from_ptr", [
let hasVerifier = 1;
}
+//===--===//
+// GatherOp
+//===--===//
+
+def Ptr_
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From b60b806cae55aa12437ff99ad2b1f6c3d3c8da34 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From fd7e685e86a7f20048293d8bb9f5a60b613b3737 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156406
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>From 8b1424a14a78d15c2ecb356cdc4df80a796a0050 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/tobias-stadler created
https://github.com/llvm/llvm-project/pull/156357
None
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@@ -17,6 +17,46 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
include "mlir/Interfaces/ViewLikeInterface.td"
include "mlir/IR/OpAsmInterface.td"
+//===--===//
+// Common props
+//===
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From c82858d3ba2267af6638e29d2601715b582a2968 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 26edc73312a06af78a0e3d31f86a2c5bcf97f734 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
@@ -633,13 +633,30 @@ class InlayHintVisitor : public
RecursiveASTVisitor {
}
if (auto *AT = D->getType()->getContainedAutoType()) {
- if (AT->isDeduced() && !D->getType()->isDependentType()) {
-// Our current approach is to place the hint on the variable
s-barannikov wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156360?utm_source=stack-comment-downstack-mergeability-warn
https://github.com/boomanaiden154 created
https://github.com/llvm/llvm-project/pull/156533
Subshells are not supported in the lit internal shell. We can remove
them by constructing sed commands directly inside of a separate file.
Towards #102700.
_
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156581
This will make it easier to precisely express operand constraints
without having the implicit getLdStRegisterOperand at the bottom.
Also prunes out using AV classes in some instructions where AGPRs
are not relevan
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156580
Start stripping out the uses of getLdStRegisterOperand. This
added a confusing level of indirection where the class at the
definition point was not the actual class used. This was also
pulling in the AV class usag
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156581?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156580?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156581
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https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From 0be0b1335e8855e4e128edcd4661888c299d1287 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analys
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133537
>From e728f3444624a5f47f0af84c21fb3a584f3e05b7 Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Fri, 1 Aug 2025 17:27:41 -0700
Subject: [PATCH] Add verifier check
Created using spr 1.3.6-beta.1
---
llvm/lib
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156420
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zhaoqi5 wrote:
Ping.
https://github.com/llvm/llvm-project/pull/151634
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https://github.com/llvm/llvm-project/pull/156361
>From 6ff221b947f637f100c1e8db3d2df2651beff3af Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153026
>From 46f04e8aefd98d782131616030857eb51dc8b1fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:12:49 +0900
Subject: [PATCH 1/2] AMDGPU: Add tests for every mfma intrinsic v-to-a mapping
M
https://github.com/MaskRay approved this pull request.
https://github.com/llvm/llvm-project/pull/156538
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153025
>From e9015799806374bc266257627df96ae2c2dfd43e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:05:44 +0900
Subject: [PATCH] AMDGPU: Add test for mfma rewrite pass respecting optnone
---
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/156170
>From 51081359fa4a76c9d20489084ce2a399b5bfc520 Mon Sep 17 00:00:00 2001
From: Shashi Shankar
Date: Sat, 30 Aug 2025 11:56:03 +0200
Subject: [PATCH 1/2] [AArch64][BTI] Add BTI at EH entries. (#155308)
Mark EH
https://github.com/Pierre-vh approved this pull request.
Add NFC to the title?
https://github.com/llvm/llvm-project/pull/156405
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https://github.com/llvm/llvm-project/pull/155607
>From 96904665ffd481eab0087e1a7c2edcc6ef0bb915 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153026
>From 46f04e8aefd98d782131616030857eb51dc8b1fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:12:49 +0900
Subject: [PATCH 1/2] AMDGPU: Add tests for every mfma intrinsic v-to-a mapping
M
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153025
>From e9015799806374bc266257627df96ae2c2dfd43e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:05:44 +0900
Subject: [PATCH] AMDGPU: Add test for mfma rewrite pass respecting optnone
---
https://github.com/petrhosek approved this pull request.
https://github.com/llvm/llvm-project/pull/156533
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https://github.com/llvm/llvm-project/pull/155992
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https://github.com/llvm/llvm-project/pull/156284
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https://github.com/devnexen approved this pull request.
https://github.com/llvm/llvm-project/pull/156303
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github-actions[bot] wrote:
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Zingam wrote:
@frederick-vs-ja If this isn't landing in LLVM21? Can you update the release
notes, etc.
https://github.com/llvm/llvm-project/pull/151808
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https://github.com/llvm/llvm-project/pull/156405
This helps shrink the diff in a future change.
>From c3c9b84d25cec1357823ca94dfc9873b941746c4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 2 Sep 2025 14:06:22 +0900
Subject: [PATCH] AMDGPU: Reorder a
https://github.com/joker-eph approved this pull request.
https://github.com/llvm/llvm-project/pull/156368
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usx95 wrote:
I think the liveness analysis can be built on top of this. A UseFact with a
write `a = b` kills value in `a` and gens value of `b`. All other facts
essentially gens the origins involved. WDYT ?
https://github.com/llvm/llvm-project/pull/154316
__
@@ -559,9 +553,49 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+
https://github.com/HighCommander4 created
https://github.com/llvm/llvm-project/pull/156404
Fixes https://github.com/clangd/clangd/issues/2478
>From 7c8f310155914c17e8e3c6d485acb4464800ddd1 Mon Sep 17 00:00:00 2001
From: Nathan Ridge
Date: Tue, 2 Sep 2025 01:06:07 -0400
Subject: [PATCH] [clang]
https://github.com/zhaoqi5 updated
https://github.com/llvm/llvm-project/pull/151634
>From 29e45d02001d415207d4a05b3d8a398674939b19 Mon Sep 17 00:00:00 2001
From: Qi Zhao
Date: Fri, 1 Aug 2025 11:30:19 +0800
Subject: [PATCH 1/2] [LoongArch] Use xvperm.w for cross-lane access within a
single vec
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156430
Backport ba707db840516b2246c6a31ef8a96e41939deeb5
Requested by: @nikic
>From 543fc154306659f184bb82082b414eaf4536cbf0 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim
Date: Tue, 2 Sep 2025 09:44:15 +0100
Subject:
https://github.com/joker-eph approved this pull request.
LG overall
https://github.com/llvm/llvm-project/pull/156355
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@@ -56,6 +96,58 @@ def Ptr_FromPtrOp : Pointer_Op<"from_ptr", [
let hasVerifier = 1;
}
+//===--===//
+// GatherOp
+//===--===//
+
+def Ptr_
@@ -56,6 +96,58 @@ def Ptr_FromPtrOp : Pointer_Op<"from_ptr", [
let hasVerifier = 1;
}
+//===--===//
+// GatherOp
+//===--===//
+
+def Ptr_
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/156430
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llvmbot wrote:
@phoebewang What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/156430
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https://github.com/joker-eph approved this pull request.
https://github.com/llvm/llvm-project/pull/156368
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https://github.com/Xazax-hun edited
https://github.com/llvm/llvm-project/pull/154316
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https://github.com/Xazax-hun commented:
Overall looks good, some small questions inline.
https://github.com/llvm/llvm-project/pull/154316
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@@ -556,8 +554,47 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+
@@ -556,8 +554,47 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+
Xazax-hun wrote:
> I think the liveness analysis can be built on top of this.
I see! I was not sure what the layering would be. Makes sense to me.
https://github.com/llvm/llvm-project/pull/154316
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@@ -556,8 +554,47 @@ class FactGeneratorVisitor : public
ConstStmtVisitor {
return false;
}
+ void handleAssignment(const Expr *LHSExpr, const Expr *RHSExpr) {
+// Find the underlying variable declaration for the left-hand side.
+if (const auto *DRE_LHS =
+
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156462
Backport e591df63e583a39b2b8356dae7024df82d2f2204
Requested by: @DavidSpickett
>From 6ee50cd80cc912d5b0906399aad7166f79e7a10d Mon Sep 17 00:00:00 2001
From: David Spickett
Date: Tue, 2 Sep 2025 15:13:03 +0100
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/156462
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155560
>From 493b50264a7f348de647e9817fbd2dcbff81b95a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:17:00 +0900
Subject: [PATCH] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc
This a
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From bc2070b9e0d85b51ddff16ee22faac470afbce53 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
This is in
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155607
>From 2ee13abfc257a65f5723039c3419371a6cb50ad6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155603
>From 5c284f46a1063d5d0788c25a0d37ba019c171d54 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 16:19:23 +0900
Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in
usesConstan
@@ -4447,76 +4447,76 @@
# GFX11: ds_store_b128 v255, v[2:5] offset:65535 ; encoding:
[0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00
-# GFX11: ds_store_b16 v0, v1 ; encoding:
[0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
+# G
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From bc2070b9e0d85b51ddff16ee22faac470afbce53 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
This is in
https://github.com/steakhal updated
https://github.com/llvm/llvm-project/pull/154738
>From 656763c898bff7783d87ed7d17c3050c631fe06d Mon Sep 17 00:00:00 2001
From: Aaron Ballman
Date: Fri, 1 Aug 2025 12:31:56 -0400
Subject: [PATCH] [Analyzer] No longer crash with VLA operands to unary type
trai
@@ -2850,6 +2850,12 @@ def int_experimental_convergence_anchor
def int_experimental_convergence_loop
: DefaultAttrsIntrinsic<[llvm_token_ty], [], [IntrNoMem, IntrConvergent]>;
+//===- Structure Protection Intrinsics
===//
+
+def int_prote
@@ -461,6 +463,162 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses(
return Changed;
}
+namespace {
+
+enum class PointerEncoding {
+ Rotate,
+ PACCopyable,
+ PACNonCopyable,
+};
+
+bool expandProtectedFieldPtr(Function &Intr) {
+ Module &M = *Intr.getParent();
+
@@ -461,6 +463,162 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses(
return Changed;
}
+namespace {
+
+enum class PointerEncoding {
+ Rotate,
+ PACCopyable,
+ PACNonCopyable,
+};
+
+bool expandProtectedFieldPtr(Function &Intr) {
+ Module &M = *Intr.getParent();
+
@@ -0,0 +1,167 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
+; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck
--check-prefix=NOPAUTH %s
+; RUN: opt -passes=pre-isel-intrinsic-lowering -m
@@ -461,6 +463,162 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses(
return Changed;
}
+namespace {
+
+enum class PointerEncoding {
+ Rotate,
+ PACCopyable,
+ PACNonCopyable,
+};
nikic wrote:
Unused?
https://github.com/llvm/llvm-project/pull/151
@@ -461,6 +463,162 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses(
return Changed;
}
+namespace {
+
+enum class PointerEncoding {
+ Rotate,
+ PACCopyable,
+ PACNonCopyable,
+};
+
+bool expandProtectedFieldPtr(Function &Intr) {
+ Module &M = *Intr.getParent();
+
@@ -697,8 +697,7 @@ static bool isSafeAndProfitableToSinkLoad(LoadInst *L) {
Instruction *InstCombinerImpl::foldPHIArgLoadIntoPHI(PHINode &PN) {
LoadInst *FirstLI = cast(PN.getIncomingValue(0));
- // Can't forward swifterror through a phi.
- if (FirstLI->getOperand(0)->isS
llvmbot wrote:
@hubert-reinterpretcast What do you think about merging this PR to the release
branch?
https://github.com/llvm/llvm-project/pull/156502
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156505
Backport 63195d3d7a8bde05590f91a38398f986bb4265b2
3e6ec475b756559560cba4a16c2bc755aa8caee5
Requested by: @amy-kwan
>From 7df62021a2bcceff725ec5bb24960bf987711f4b Mon Sep 17 00:00:00 2001
From: David Tenty
Dat
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/156505
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llvmbot wrote:
@hubert-reinterpretcast What do you think about merging this PR to the release
branch?
https://github.com/llvm/llvm-project/pull/156505
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/156405
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llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Nathan Ridge (HighCommander4)
Changes
Fixes https://github.com/clangd/clangd/issues/2478
---
Full diff: https://github.com/llvm/llvm-project/pull/156404.diff
2 Files Affected:
- (modified) clang/lib/Sema/HeuristicResolver.cpp (+19)
- (
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From ed950c319568da2a902fde1f1899e9cdbbebf7cb Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From d3e77cd38331d0e492c704ac3073ec084be88b21 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 46fc93b95a9607f4b9c5f8883c313d94ef519d65 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From d3e77cd38331d0e492c704ac3073ec084be88b21 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From b62d8435beaf6fda78ff37f10152159426891d95 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 4188fa46342e6747f985d232677f6a690fa9972c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From b62d8435beaf6fda78ff37f10152159426891d95 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 95a0d748eae948d6c520dd4706cac52cc830ecfd Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From 05821956deebe21b8dd2bdd0a5962a0987d42775 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
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