[RFC] RISC-V: Support -mcmodel=large.

This is a RFC patch for large code model implementation. gcc/ChangeLog: * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF and LABEL_REF type. (call_insn_operand): Support for CM_Large. (pcrel_symbol_operand): New. * gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_d

[PATCH] RISC-V:Raname UNSPEC_CLMUL in vector-crypto.md

UNSPEC_CLMUL is defined to define_c_enum in riscv.md, so it shouldn't be redefined to define_int_iterator again. *gcc/ChangeLog:* * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to UNSPEC_CLMUL_VC. 0001-RISC-V-Raname-UNSPEC_CLMUL-in-vector-crypto.md.patch Description: Binary data

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BOUNDARY. Please find attached. Thank you. Jeff Law 於 2023年12月18日 週一 上午3:15寫道： > > > On 11/10/23 02:10, KuanLin Chen wrote: > > Sorry. I

[PATCH][V4] RISC-V: Nan-box the result of movhf on soft-fp16

According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/ri

[PATCH][V3] RISC-V: Nan-box the result of movhf on soft-fp16

According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/ri

[PATCH] RISC-V: Nan-box the result of movhf on soft-fp16

According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/r

[RFC][V2] RISC-V: Support -mcmodel=large.

gcc/ChangeLog: * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF and LABEL_REF type. (call_insn_operand): Support for CM_Large. (pcrel_symbol_operand): New. * gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define "__riscv_cmodel_large". * gcc/config/riscv/riscv-op

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

Sorry. It missed a semicolon in the previos patch. Please find the new one in the attachment. Thanks. 0001-RISC-V-Support-mcmodel-large.patch Description: Binary data

[PATCH][V2] RISC-V: Nan-box the result of movhf on soft-fp16

According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/ri

[PATCH] RISC-V: Remove skip of decl in registered_function.

The GTY skip makes GGC clean the registered functions wrongly in lto. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c -O2 -march=rv64gcv In file included from bug-3.c:2: internal compiler error: Segmentation fault gcc/ChangeLog: *riscv-vector-built

[PATCH] RISC-V: Fix rvv builtin function groups registration asynchronously.

In the origin, cc1 registers rvv builtins with turn on all sub vector extensions but lto not. It makes lto use the asynchronous DECL_MD_FUNCTION_CODE from lto-objects. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c -O2 -march=rv64gcv bug-3.c: In function '

[PATCH 2/3] Add one more argument to simulate_builtin_function_decl.

simulate_builtin_function_decl may return decl that be ggc_freed already in pushdecl when duplicate_decls is true. Add a argument CREATE_P for the caller to know if the return decl is usable. gcc/ChangeLog: * langhooks.h (simulate_builtin_function_decl): Add one more argument.

[PATCH v2 1/3] RISC-V: Remove skip of decl in registered_function.

Hi Jeff, I'm really sorry for the regression failure. I missed one patch to fix these issues. Thanks for your review. The GTY skip makes GGC clean the registered functions wrongly in lto. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c -O2 -march=rv64gcv

[PATCH 3/3] RISC-V: Fix rvv builtin function groups registration

In the origin, cc1 registers rvv builtins with turn on all sub vector extensions but lto not. It makes lto use the asynchronous DECL_MD_FUNCTION_CODE from lto-objects. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c -O2 -march=rv64gcv bug-10.c: In function

[PATCH 2/7] RISC-V: Add support for the XAndesperf ISA extension.

Hi, This patch adds support for the XAndesperf ISA extension. The 32-bit AndeStar V5 extension includes branch instructions, load effective address instructions, and string processing instructions for performance improvement. New INSN patterns are added into the new file andes.md as a seprated ven

[PATCH 7/7] RISC-V: Add support for the XAndesvdot ISA extension.

Hi, This extension defines vector instructions to calculae of the signed/unsigned dot product of four SEW/4-bit data and accumulate the result into a SEWbit element for all elements in a vector register. gcc/ChangeLog: * config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New class

[PATCH 3/7] RISC-V: Add support for the XAndesbfhcvt ISA extension.

Hi, This extension defines instructions to perform scalar floating-point conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit single-precision floating-point (SP) data in a scalar floating point register. gcc/ChangeLog: * config/riscv/andes.def: Add nds_fcvt_s_bf16

[PATCH 4/7] RISC-V: Add support for the XAndesvbfhcvt ISA extension.

Hi, This patch add support for XAndesvbfhcvt ISA extension. This extension defines instructions to perform vector floating-point conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit single-precision floating-point (SP) data in a vector register. gcc/ChangeLog: * co

[PATCH 6/7] RISC-V: Add support for the XAndesvpackfph ISA extension.

Hi, This extension defines vector instructions to extract a pair of FP16 data from a floating-point register. Multiply the top FP16 data with the FP16 elements and add the result with the bottom FP16 data. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Turn on VECTOR_ELEN_

[PATCH 1/7] RISC-V: Add basic XAndes vendor extension support.

Hi, This is a patch series for Andes vender extension of RISC-V. These patches are tested by riscv-gnu-toolchain gcc/g++ testsuite. And the report is the same as without these patches. = Summary of gcc testsuite = | # of unexpected case /

[PATCH 5/7] RISC-V: Add support for the XAndesvsintload ISA

Hi, This extension defines vector load instructions to move sign-extended or zero-extended INT4 data into 8-bit vector register elements. gcc/ChangeLog: * config/riscv/andes-vector-builtins-bases.cc (nds_nibbleload): New class. * config/riscv/andes-vector-builtins-bases.h

Re: [PATCH] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid

Hi Juzhe, I think fault_load_def::get_name should remove "instance.pred == PRED_TYPE_mu", right? 於 2023年6月2日 週五 上午7:05寫道： > > From: Juzhe-Zhong > > Base on these: > https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/232 > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/233 > > Ad