[Bug rtl-optimization/93974] [10 Regression] ICE in decompose_normal_address, at rtlanal.c:6403 on powerpc64le-linux-gnu since r10-6762

2020-03-06 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93974 --- Comment #15 from rsandifo at gcc dot gnu.org --- (In reply to Peter Bergner from comment #14) > (In reply to Vladimir Makarov from comment #13) > > Sorry, I have no good knowledge of decompose_address. The original author >

[Bug target/94072] [10 Regression] ICE: SIGSEGV due to infinite recursion in expand_expr/expand_expr_real_1 with -msve-vector-bits=512 since r10-4197

2020-03-17 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94072 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED

[Bug target/94201] aarch64:ICE in tiny code model for ilp32

2020-03-19 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94201 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug target/94072] [10 Regression] ICE: SIGSEGV due to infinite recursion in expand_expr/expand_expr_real_1 with -msve-vector-bits=512 since r10-4197

2020-03-20 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94072 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug tree-optimization/94261] New: [10 Regression] ICE in vect_get_vec_def_for_operand_1 for 3-element condition reduction

2020-03-22 Thread rsandifo at gcc dot gnu.org
Keywords: ice-on-valid-code Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org CC: rguenth at gcc dot gnu.org Target Milestone

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 rsandifo at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 --- Comment #4 from rsandifo at gcc dot gnu.org --- The cycling comes from reloading: (insn 7 6 8 2 (set (reg:SD 122 [ a32 ]) (mem/c:SD (reg/f:DI 120) [1 a32+0 S4 A32])) "gcc/testsuite/gcc.target/powerpc/pr39902-2.c"

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 --- Comment #5 from rsandifo at gcc dot gnu.org --- (In reply to Zdenek Sojka from comment #1) > I observe the same issue, and it breaks libgcc build for me: What configure arguments do you use?

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 --- Comment #7 from rsandifo at gcc dot gnu.org --- Created attachment 48080 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48080&action=edit Proof-of-concept hack to back up the point in comment 4 This hack shows what I mean in

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 --- Comment #9 from rsandifo at gcc dot gnu.org --- (In reply to Segher Boessenkool from comment #8) > SFmode values are stored as DP IEEE float normally. There may be other > cases as well, but this is the obvious one. OK, thanks. Do

[Bug tree-optimization/94261] [10 Regression] ICE in vect_get_vec_def_for_operand_1 for 3-element condition reduction

2020-03-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94261 --- Comment #5 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #3) > (In reply to Richard Biener from comment #2) > > when placing gcc_unreachable () at the swapping place and most testcases > >

[Bug tree-optimization/94261] [10 Regression] ICE in vect_get_vec_def_for_operand_1 for 3-element condition reduction

2020-03-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94261 --- Comment #7 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #6) > (In reply to rsand...@gcc.gnu.org from comment #5) > > (In reply to Richard Biener from comment #3) > > > (In reply to R

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 rsandifo at gcc dot gnu.org changed: What|Removed |Added Attachment #48080|0 |1 is obsolete

[Bug target/94254] [10 regression] r10-7312 causes compiler hangs

2020-03-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94254 --- Comment #13 from rsandifo at gcc dot gnu.org --- (In reply to Segher Boessenkool from comment #12) > That patch looks fine, thank you! > > Is there some way you can test if this works? Ideally in the testsuite > of course, but

[Bug tree-optimization/94398] ICE: in vectorizable_load, at tree-vect-stmts.c:9173

2020-03-30 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94398 --- Comment #3 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #2) > But the ICE happens because the result from the function at transform time > does not match that at analysis time. > > Richard?

[Bug tree-optimization/94398] ICE: in vectorizable_load, at tree-vect-stmts.c:9173

2020-03-30 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94398 rsandifo at gcc dot gnu.org changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed

[Bug rtl-optimization/92989] [10 Regression] The mips-mti-linux-gnu fails to build after r276327

2020-04-03 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92989 --- Comment #10 from rsandifo at gcc dot gnu.org --- (In reply to Jakub Jelinek from comment #9) > Richard, could you please have a look again? OK, I'll try to get to this early next week.

[Bug rtl-optimization/92989] [10 Regression] The mips-mti-linux-gnu fails to build after r276327

2020-04-03 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92989 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|REOPENED|ASSIGNED

[Bug rtl-optimization/92989] [10 Regression] The mips-mti-linux-gnu fails to build after r276327

2020-04-05 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92989 rsandifo at gcc dot gnu.org changed: What|Removed |Added URL||https://gcc.gnu.org

[Bug rtl-optimization/92989] [10 Regression] The mips-mti-linux-gnu fails to build after r276327

2020-04-06 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92989 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug rtl-optimization/94605] New: [8/9/10 Regression] ICE in early-remat.c:process_block with multi-output asms

2020-04-15 Thread rsandifo at gcc dot gnu.org
: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling the following testcase with -O2 -march=armv8.2-a+sve: typedef int

[Bug rtl-optimization/94605] [8/9/10 Regression] ICE in early-remat.c:process_block with multi-output asms

2020-04-15 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94605 rsandifo at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot

[Bug target/94606] [10 Regression] ICE creating fixed-length SVE predicate

2020-04-15 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED

[Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate

2020-04-15 Thread rsandifo at gcc dot gnu.org
Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling the following testcase with -O3 -march=armv8.2-a+sve -msve

[Bug target/94606] [10 Regression] ICE creating fixed-length SVE predicate

2020-04-16 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug target/94668] New: [10 Regression] ICE generating float vec_inits since r10-808

2020-04-20 Thread rsandifo at gcc dot gnu.org
Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling the following with -O -march=armv8.2-a+sve -msve-vector

[Bug target/94668] [10 Regression] ICE generating float vec_inits since r10-808

2020-04-20 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94668 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever

[Bug target/94668] [10 Regression] ICE generating float vec_inits since r10-808

2020-04-20 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94668 rsandifo at gcc dot gnu.org changed: What|Removed |Added Target Milestone|--- |10.0

[Bug target/94668] [10 Regression] ICE generating float vec_inits since r10-808

2020-04-20 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94668 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED Status

[Bug tree-optimization/94683] New: ICE in forwprop when folding to a VEC_PERM_EXPR

2020-04-21 Thread rsandifo at gcc dot gnu.org
: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Compiling this with -march=armv8.2-a+sve -msve-vector-bits=256 -O3: #include typedef float v8sf __attribute__((vector_size(32))); svfloat32_t f (svbool_t pg

[Bug tree-optimization/94683] ICE in forwprop when folding to a VEC_PERM_EXPR

2020-04-21 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94683 rsandifo at gcc dot gnu.org changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed

[Bug tree-optimization/94683] ICE in forwprop when folding to a VEC_PERM_EXPR

2020-04-21 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94683 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug tree-optimization/94700] New: ICE in forwprop when folding to a VEC_PERM_EXPR

2020-04-21 Thread rsandifo at gcc dot gnu.org
: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Compiling this with -march=armv8.2-a+sve -msve-vector-bits=256 -O3: #include typedef float v8sf __attribute__((vector_size(32))); svfloat32_t f (svbool_t pg

[Bug tree-optimization/94700] ICE in forwprop when folding to a VEC_PERM_EXPR

2020-04-21 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94700 rsandifo at gcc dot gnu.org changed: What|Removed |Added Keywords||ice-on-valid-code

[Bug tree-optimization/94700] ICE in forwprop when folding to a VEC_PERM_EXPR

2020-04-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94700 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED Status

[Bug target/94678] aarch64: unexpected result with -mgeneral-regs-only and sve

2020-04-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94678 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug c/94712] aarch64:Adjust some testcases for ilp32 option conflict

2020-04-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94712 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug tree-optimization/94727] [10 Regression] GCC produces incorrect code with -O3 since r10-5071-g02d895504cc59be0

2020-04-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94727 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED

[Bug tree-optimization/94727] [10 Regression] GCC produces incorrect code with -O3 since r10-5071-g02d895504cc59be0

2020-04-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94727 --- Comment #5 from rsandifo at gcc dot gnu.org --- Well, this is a bit of mess (surprise). We have a "<" comparison between two booleans that are leaves of the SLP tree, so vectorizable_comparison falls back on: /* Invaria

[Bug tree-optimization/94727] [10 Regression] GCC produces incorrect code with -O3 since r10-5071-g02d895504cc59be0

2020-04-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94727 --- Comment #7 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #6) > (In reply to rsand...@gcc.gnu.org from comment #5) > > > > However, we then defer to vect_get_slp_defs to get the actual op

[Bug tree-optimization/94727] [10 Regression] GCC produces incorrect code with -O3 since r10-5071-g02d895504cc59be0

2020-04-23 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94727 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug tree-optimization/94784] ICE: in simplify_vector_constructor, at tree-ssa-forwprop.c:2482

2020-04-27 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94784 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug target/94852] -ffloat-store on x64 target

2020-04-30 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94852 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|RESOLVED|NEW CC

[Bug tree-optimization/94899] Failure to optimize out add before compare with INT_MIN

2020-05-01 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94899 rsandifo at gcc dot gnu.org changed: What|Removed |Added Keywords||easyhack

[Bug rtl-optimization/94873] [8/9/10/11 Regression] wrong code with -O -fno-merge-constants -fno-split-wide-types -fno-tree-fre

2020-05-01 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94873 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug rtl-optimization/94873] [8/9/10/11 Regression] wrong code with -O -fno-merge-constants -fno-split-wide-types -fno-tree-fre

2020-05-01 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94873 --- Comment #8 from rsandifo at gcc dot gnu.org --- (In reply to Segher Boessenkool from comment #7) > REG_EQ* is documented as only being allowed on insns that set only one > register. If you want to change that, you'll have to

[Bug middle-end/94941] New: Expansion of some internal fns can drop the lhs on the floor

2020-05-04 Thread rsandifo at gcc dot gnu.org
Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- internal-fn.c:expand_mask_load_optab_fn uses expand_insn to emit the load instruction, but doesn't

[Bug middle-end/94941] Expansion of some internal fns can drop the lhs on the floor

2020-05-04 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94941 rsandifo at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2020-05-04 Ever

[Bug rtl-optimization/94873] [8/9/10/11 Regression] wrong code with -O -fno-merge-constants -fno-split-wide-types -fno-tree-fre

2020-05-04 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94873 --- Comment #11 from rsandifo at gcc dot gnu.org --- (In reply to Segher Boessenkool from comment #9) > "clobber" is a red herring; it is impossible to make a REG_EQ* note for > a clobber, a clobber does not set a new value (t

[Bug middle-end/94941] Expansion of some internal fns can drop the lhs on the floor

2020-05-04 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94941 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED Status

[Bug rtl-optimization/94873] [8/9/10/11 Regression] wrong code with -O -fno-merge-constants -fno-split-wide-types -fno-tree-fre

2020-05-04 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94873 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||ebotcazou at gcc dot

[Bug target/92469] ICE: output_operand: invalid use of register 'frame' in 7/8/9/10

2020-05-05 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92469 --- Comment #10 from rsandifo at gcc dot gnu.org --- "jakub at gcc dot gnu.org" writes: > --- Comment #9 from Jakub Jelinek --- > Seems neither accessible_reg_set nor operand_reg_set can exclude frame, > because >

[Bug target/94980] [8/9/10/11 Regression] ICE: verify_gimple failed: position plus size exceeds size of referenced object in 'bit_field_ref' with -mavx512vl

2020-05-07 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94980 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED

[Bug target/94980] [8/9/10/11 Regression] ICE: verify_gimple failed: position plus size exceeds size of referenced object in 'bit_field_ref' with -mavx512vl

2020-05-12 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94980 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug target/95105] New: Bogus reference-compatibility error for arm_sve_vector_bits

2020-05-13 Thread rsandifo at gcc dot gnu.org
Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling this testcase with -march=armv8.2-a+sve -msve-vector-bits=512

[Bug target/95105] Bogus reference-compatibility error for arm_sve_vector_bits

2020-05-13 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95105 rsandifo at gcc dot gnu.org changed: What|Removed |Added Ever confirmed|0 |1 Target Milestone

[Bug middle-end/95114] New: [9/10/11 Regression] ICE in obj_type_ref_class for structural-equality types

2020-05-13 Thread rsandifo at gcc dot gnu.org
-on-valid-code Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org CC: hubicka at gcc dot gnu.org Target Milestone: --- Target: aarch64

[Bug middle-end/95114] [9/10/11 Regression] ICE in obj_type_ref_class for structural-equality types

2020-05-13 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95114 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Target

[Bug target/92658] x86 lacks vector extend / truncate

2020-05-14 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92658 --- Comment #12 from rsandifo at gcc dot gnu.org --- (In reply to rguent...@suse.de from comment #11) > On Thu, 14 May 2020, ubizjak at gmail dot com wrote: > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92658 > > > &

[Bug target/94991] aarch64: ICE: Segmentation fault with option -mgeneral-regs-only

2020-05-18 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94991 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED CC

[Bug target/95125] Unoptimal code for vectorized conversions

2020-05-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95125 --- Comment #8 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #7) > (In reply to Uroš Bizjak from comment #6) > > (In reply to Hongtao.liu from comment #5) > > > (In reply to Uroš Bizj

[Bug target/95341] New: Poor vector_size decomposition when SVE is enabled

2020-05-26 Thread rsandifo at gcc dot gnu.org
: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling the following with -O2 -march=armv8-a: typedef unsigned int uint_vec __attribute__((vector_size(32))); uint_vec f1

[Bug target/95341] Poor vector_size decomposition when SVE is enabled

2020-05-26 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95341 --- Comment #3 from rsandifo at gcc dot gnu.org --- (In reply to ktkachov from comment #2) > Interestingly, -msve-vector-bits gives good codegen for 128, 256, 512 but > bad for 1024, 2048 and VLA code That's because addition

[Bug target/95361] New: Segfault when generating an epilogue for a partly-shrinked-wrapped SVE frame

2020-05-27 Thread rsandifo at gcc dot gnu.org
: ice-on-valid-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Compiling the following with -O2 -march=armv8.2+sve

[Bug target/95361] Segfault when generating an epilogue for a partly-shrinked-wrapped SVE frame

2020-05-27 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95361 rsandifo at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2020-05-27

[Bug target/95459] aarch64: ICE in in aarch64_short_vector_p, at config/aarch64/aarch64.c:16803

2020-06-01 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95459 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug target/95459] aarch64: ICE in aarch64_short_vector_p, at config/aarch64/aarch64.c:16803

2020-06-02 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95459 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug target/95523] aarch64:ICE in register_tuple_type,at config/aarch64/aarch64-sve-builtins.cc:3434

2020-06-04 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95523 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug target/95523] aarch64:ICE in register_tuple_type,at config/aarch64/aarch64-sve-builtins.cc:3434

2020-06-04 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95523 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|WAITING |NEW --- Comment #3 from

[Bug middle-end/95528] [10/11 Regression] internal compiler error: in emit_move_insn, at expr.c:3814

2020-06-05 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95528 --- Comment #6 from rsandifo at gcc dot gnu.org --- (In reply to Jakub Jelinek from comment #4) > I'd say the vectorizer/simplify_vector_constructor just shouldn't attempt to > use these (e.g. vec_pack*, vec_unpack* optabs)

[Bug middle-end/95528] [10/11 Regression] internal compiler error: in emit_move_insn, at expr.c:3814

2020-06-05 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95528 --- Comment #7 from rsandifo at gcc dot gnu.org --- (In reply to rsand...@gcc.gnu.org from comment #6) > In summary: from an AArch64 perspective, it's probably fine to > check !VECTOR_MODE_P || VECTOR_BOOLEAN_TYPE_P. But given the

[Bug target/95254] aarch64: gcc generate inefficient code with fixed sve vector length

2020-06-05 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95254 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED CC

[Bug middle-end/95528] [10/11 Regression] internal compiler error: in emit_move_insn, at expr.c:3814

2020-06-05 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95528 --- Comment #9 from rsandifo at gcc dot gnu.org --- (In reply to Jakub Jelinek from comment #8) > Created attachment 48683 [details] > gcc11-pr95528.patch > > Untested fix. The VECTOR_TYPE_P condition should be redundant. Look

[Bug target/95523] aarch64:ICE in register_tuple_type,at config/aarch64/aarch64-sve-builtins.cc:3434

2020-06-10 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95523 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED

[Bug tree-optimization/95570] vect: ICE: Segmentation fault in vect_loop_versioning

2020-06-12 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95570 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED

[Bug tree-optimization/95694] [9/10/11 Regression] ICE in trunc_int_for_mode, at explow.c:59 since r9-7156-g33579b59aaf02eb7

2020-06-16 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95694 rsandifo at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot

[Bug tree-optimization/95199] Remove extra variable created for memory reference in loop vectorization.

2020-06-17 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95199 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED Status

[Bug c++/95726] ICE with aarch64 __Float32x4_t as template argument

2020-06-17 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95726 --- Comment #2 from rsandifo at gcc dot gnu.org --- (In reply to Jason Merrill from comment #1) > Does the aarch64 port expect __Float32x4_t type to be considered equivalent > to the GNU vector type or not? If so, w

[Bug c++/95726] ICE with aarch64 __Float32x4_t as template argument

2020-06-18 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95726 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED

[Bug c++/95726] ICE with aarch64 __Float32x4_t as template argument

2020-06-18 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95726 --- Comment #4 from rsandifo at gcc dot gnu.org --- (In reply to Jakub Jelinek from comment #3) > But if they mangle differently, then structural_comptypes shouldn't treat > them as same types. That certainly avoids the ICE, and

[Bug c++/95726] ICE with aarch64 __Float32x4_t as template argument

2020-06-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95726 --- Comment #8 from rsandifo at gcc dot gnu.org --- Thanks for the pointers. Putting the mangled name in a target-specific attribute (like we do for SVE) seems to fix it. It actually also keeps the testcase in comment 4 “working”, which is

[Bug bootstrap/95805] [11 regression] gcc/recog.h:301:30: error: too many arguments to function call, expected 1, have 2

2020-06-22 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95805 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug target/95674] Unnecessary move when doing division-by-multiplication

2020-06-27 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95674 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot

[Bug target/95958] New: [meta-bug] Inefficient arm_neon.h code for AArch64

2020-06-29 Thread rsandifo at gcc dot gnu.org
Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* This meta-bug is to collect AArch64 performance improvements that require or have a strong relationship

[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64

2020-06-29 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 rsandifo at gcc dot gnu.org changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed

[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64

2020-06-29 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 rsandifo at gcc dot gnu.org changed: What|Removed |Added Keywords||missed-optimization

[Bug target/95962] New: Inefficient code for simple arm_neon.h iota operation

2020-06-29 Thread rsandifo at gcc dot gnu.org
: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Blocks: 95958 Target Milestone: --- Target: aarch64*-*-* For: #include int32x4_t foo (void) { int32_t array[] = { 0, 1

[Bug target/95964] New: AArch64 arm_neon.h arithmetic functions lack appropriate attributes

2020-06-29 Thread rsandifo at gcc dot gnu.org
-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Blocks: 95958 Target Milestone: --- Target: aarch64*-*-* For

[Bug target/95964] AArch64 arm_neon.h arithmetic functions lack appropriate attributes

2020-06-29 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95964 --- Comment #2 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #1) > You could use fnspec attributes to improve things but of course open-coding > those as GIMPLE is preferable (last resort is to "fold

[Bug target/95967] New: Poor aarch64 vector constructor code when using arm_neon.h

2020-06-29 Thread rsandifo at gcc dot gnu.org
Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Depends on: 95962 Blocks: 95958 Target Milestone: --- Target: aarch64*-*-* We generate poor code for the attached functions: f1

[Bug target/95967] Poor aarch64 vector constructor code when using arm_neon.h

2020-06-29 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95967 --- Comment #1 from rsandifo at gcc dot gnu.org --- Created attachment 48802 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48802&action=edit 6 constructor functions This time with attachment -- not sure what happened last time.

[Bug target/95969] New: Use of __builtin_aarch64_im_lane_boundsi in AArch64 arm_neon.h interferes with gimple optimisation

2020-06-29 Thread rsandifo at gcc dot gnu.org
Keywords: missed-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Blocks: 95958 Target Milestone: --- Target: aarch64

[Bug target/95974] New: AArch64 arm_neon.h stores interfere with gimple optimisations

2020-06-29 Thread rsandifo at gcc dot gnu.org
-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Blocks: 95958 Target Milestone: --- Target: aarch64*-*-* For

[Bug c++/92789] Non-obvious ?: behaviour with structurally equivalent types

2020-06-30 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92789 --- Comment #5 from rsandifo at gcc dot gnu.org --- Keeping open since the problem also affects arm*-*-*. I don't think we should change GCC 10 and earlier though.

[Bug c++/95726] ICE with aarch64 __Float32x4_t as template argument

2020-06-30 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95726 rsandifo at gcc dot gnu.org changed: What|Removed |Added Target|aarch64-linux |aarch64*-*-* arm

[Bug tree-optimization/95961] ICE: in exact_div, at poly-int.h:2182

2020-07-02 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95961 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug tree-optimization/96075] [8/9/10/11 Regression] bogus alignment for negative step grouped access

2020-07-06 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96075 --- Comment #4 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #3) > So we end up calling get_negative_load_store_type for this group which seems > to only handle contiguous accesses but this one is single e

[Bug tree-optimization/96091] ICE during dom: tree check: expected integer_cst, have poly_int_cst in to_wide, at tree.h:5911

2020-07-07 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96091 --- Comment #3 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #2) > Why should we not have a VECTOR_CST of POLY_INT_CST elements? If > POLY_INT_CST > is not "constant" then it shouldn't

[Bug target/95105] Bogus reference-compatibility error for arm_sve_vector_bits

2020-07-08 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95105 --- Comment #3 from rsandifo at gcc dot gnu.org --- Fixed.

[Bug target/95105] Bogus reference-compatibility error for arm_sve_vector_bits

2020-07-08 Thread rsandifo at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95105 rsandifo at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED Status

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