Hi Dave and Sima,
Please pull the following nova changes and other dependencies.
There are two minor and trivial conflicts with Linus' tree [1] and the CONFIGFS
tree [2].
There is also a minor, but slightly less trivial conflict with the Rust Xarray
tree with a resolution in [3].
[1] https://lo
On 20/05/2025 04:47, Chaoyi Chen wrote:
> From: Chaoyi Chen
>
> Convert cdn-dp-rockchip.txt to yaml.
>
> Add new "port@1" property which represents the CDN DP output to keep
> the same style as the other display interfaces.
>
> This patch also changes the constraints for "phys" and "extcon". Fo
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/
On Mon, May 19, 2025 at 10:51:24AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> See commit a414fe3a2129 ("drm/msm/gem: Drop obj lock in
> msm_gem_free_object()") for justification.
I asked for a proper commit message in v4.
Only referring to a driver commit and let the people figure out how th
On 19/05/2025 15:33, Andy Shevchenko wrote:
struct device *dev from struct ili9341 is not used anywhere, remove it.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
Signal vt subsystem to redraw console when switching to dummycon
with deferred takeover enabled. Makes the console switch to fbcon
and displays the available output.
With deferred takeover enabled, dummycon acts as the placeholder
until the first output to the console happens. At that point, fbcon
From: Konrad Dybcio
Now that Adreno specifics are out of the way, use the common config
(but leave the HBB hardcoding in place until that is wired up on the
other side).
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 20 -
drivers
Reviewed-by: Maciej Falkowski
On 5/16/2025 6:06 PM, Jeff Hugo wrote:
AIC100 devices generates Reliability, Availability, Serviceability events
via MHI QAIC_STATUS channel. Support such events and print a structured
log with details of the events, and if the event describes an uncorrected
error,
priv->state);
-
- drm_modeset_drop_locks(&ctx);
- drm_modeset_acquire_fini(&ctx);
-
return 0;
}
static struct kunit_case vc4_pv_muxing_tests[] = {
KUNIT_CASE_PARAM(drm_vc4_test_pv_muxing,
---
base-commit: a5806cd506af5a7c19bcd596e4708b5c464bfd21
change-id: 20250520-drm-vc4-kunit-fixes-a681715c4409
Best regards,
--
Maxime Ripard
drm_atomic_get_connector_state (drm.mod.c:?) drm
> vc4_mock_atomic_add_output (drivers/gpu/drm/vc4/tests/vc4_mock_output.c:?)
> vc4
> drm_vc4_test_pv_muxing (drivers/gpu/drm/vc4/tests/vc4_test_pv_muxing.c:688)
> vc4
> kunit_try_run_case (lib/kunit/test.c:400) kunit
> kunit_
This is a note to let you know that I've just added the patch titled
drm/vmwgfx: Fix a deadlock in dma buf fence polling
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
dr
From: Shixiong Ou
[WHY] If the call to sysfs_create_group() fails, there is no need to
call function sysfs_remove_group().
But if calling sysfs_create_group() fails, it will go to label
'err_cleanup:' in komeda_dev_create(), and it will call
komeda_dev_destroy() laterly.
Commit 584cf613c24a ("drm/i915/dp: Reject HBR3 when sink doesn't support
TPS4") introduced a blanket rejection of HBR3 link rate when the sink does
not support TPS4. While this was intended to address instability observed
on certain eDP panels [1], the TPS4 requirement is only mandated for DPRX
and
fixed document with spelling mistake
changes made :
1. "tweeks" to "tweaks"
Signed-off-by: Rujra Bhatt
---
Documentation/fb/sstfb.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/fb/sstfb.rst b/Documentation/fb/sstfb.rst
index 88d5a52b1..6cefa974a 100644
---
On Mon, May 19, 2025 at 03:43:33PM GMT, Tomeu Vizoso wrote:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
>
> v2:
> - Adapt to new node structure (one node per core, each with its own
> IOMMU)
> - Several misc. fixes from Sebastian Reichel
>
> v3:
> - Split register block
Add the bindings for the Neural Processing Unit IP from Rockchip.
v2:
- Adapt to new node structure (one node per core, each with its own
IOMMU)
- Several misc. fixes from Sebastian Reichel
v3:
- Split register block in its constituent subblocks, and only require
the ones that the kernel woul
As discussed a lot in the past, the UBWC config must be coherent across
a number of IP blocks (currently display and GPU, but it also may/will
concern camera/video as the drivers evolve).
So far, we've been trying to keep the values reasonable in each of the
two drivers separately, but it really m
Hi
Am 20.05.25 um 13:08 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Replace ast's code for programming the hardware gamma/palette LUT
with DRM helpers. Either load provided data or program a default.
Set the individual entries with a callback.
Each gamma/palett
On 03/05/2025 00:44, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
>> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
>> masks and shifts and make the code a bit more readable.
>>
>> Signed-off-by: Krzysztof Kozlowski
>>
>> ---
>
This uses the SHMEM DRM helpers and we map right away to the CPU and NPU
sides, as all buffers are expected to be accessed from both.
v2:
- Sync the IOMMUs for the other cores when mapping and unmapping.
v3:
- Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
Reviewed-by: Jeffrey Hug
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
presence of the PCC sblk to check whether PCC is present in the hardware
or not.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drive
Hi Steven,
On 08.05.2025 11:42, Steven Price wrote:
> On 07/05/2025 17:07, Adrián Larumbe wrote:
> > This change is essentially a Panfrost port of commit a3707f53eb3f
> > ("drm/panthor: show device-wide list of DRM GEM objects over DebugFS").
> >
> > The DebugFS file is almost the same as in Panth
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:26PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
> precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
> high accuracy.
I have a h
Hi Krzysztof,
[...]
> +static ssize_t
> +vram_total_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> +{
> + struct device *dev = kobj_to_dev(kobj->parent);
> + struct intel_memory_region *mr;
> +
> + mr = intel_memory_region_by_type(kdev_minor_to_i915(dev),
> INTE
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:27PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
> to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
> 16BPP, whereas this
Hi Prabhakar,
On Mon, May 12, 2025 at 07:23:25PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the
> "rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC
> does not provide this reset line, and attempting
Hi Krzysztof,
> This series introduces a way for applications to read local memory
> information via files in the sysfs. So far the only way to do this was
> via i915_query ioctl. This is slightly less handy than sysfs for
> external users.
"So far the only way to do this was via i915_query ioctl
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:28PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
> allow additional D-PHY register configurations after enabling data and
> clock lanes. This is requ
When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
the old symbols were kept, aiming to provide a seamless migration path
when running "make olddefconfig" or "make oldconfig".
However, the old compatibility symbols are not visible. Hence unless
they are selected by another s
Hi Krzysztof,
> Introduce a CAP_PERFMON check when accessing sysfs entries related to
> local memory information. Also introduce a intel_memory_info_paranoid
> sysctl parameter, which allows the administrator to control whether the
> check is enforced.
If we decide that this patch is neede, I thin
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm
Hi Danilo,
On 5/14/2025 12:23 PM, Danilo Krummrich wrote:
> I feel like this patch utilizes the Option type way too much and
> often without actual need. Can you please also double check?
>
I found one other instance (vbios.fwsec_image). Other than that, all others are
required AFAICS.
>> +
>>
Geert Uytterhoeven writes:
Hello Geert,
> When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
> the old symbols were kept, aiming to provide a seamless migration path
> when running "make olddefconfig" or "make oldconfig".
>
> However, the old compatibility symbols are not v
Hi Tomeu,
Am Dienstag, dem 20.05.2025 um 12:27 +0200 schrieb Tomeu Vizoso:
> The NPU cores have their own access to the memory bus, and this isn't
> cache coherent with the CPUs.
>
> Add IOCTLs so userspace can mark when the caches need to be flushed, and
> also when a writer job needs to be wait
From: Konrad Dybcio
It's supposed to be on when the UBWC encoder version is >= 4.0.
Drop the per-GPU assignments.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/dri
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/d
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mike,
Could you more details about your setup, and how you were able to repro it ?
--
Regards,
Jay
From: Mikhail Gavrilov
Sent: Tuesday, May 20, 2025 5:33 AM
To: Pillai, Aurabindo ; Chung, ChiaHsuan (T
From: Hugo Villeneuve
Allow to inherit valid properties from the dsi-controller. This fixes the
following warning when adding a panel property:
rzg2lc.dtb: dsi@1085: '#address-cells', '#size-cells', 'panel@0' do not
match any of the regexes: 'pinctrl-[0-9]+'
from schema $id:
On 5/20/2025 11:01 AM, Danilo Krummrich wrote:
> On Tue, May 20, 2025 at 09:43:42AM -0400, Joel Fernandes wrote:
>> On 5/20/2025 5:30 AM, Danilo Krummrich wrote:
>>> On Tue, May 20, 2025 at 03:55:06AM -0400, Joel Fernandes wrote:
On 5/13/2025 1:19 PM, Danilo Krummrich wrote:
> On Wed, M
Some reserved memory regions might have particular memory setup or
attributes that make them good candidates for heaps.
Let's provide a heap type that will create a new heap for each reserved
memory region flagged as such.
Signed-off-by: Maxime Ripard
---
Hi,
This series is the follow-up of the
On Tue, May 20, 2025 at 07:57:36AM -0700, Rob Clark wrote:
> On Tue, May 20, 2025 at 12:23 AM Danilo Krummrich wrote:
> > On Mon, May 19, 2025 at 10:51:24AM -0700, Rob Clark wrote:
> > > diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/drm_gpuvm.c
> > > index f9eb56f24bef..1e89a98caad4 1
When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
the old symbols were kept, aiming to provide a seamless migration path
when running "make olddefconfig" or "make oldconfig".
However, the old compatibility symbols are not visible. Hence unless
they are selected by another s
Hi
Am 20.05.25 um 14:40 schrieb Geert Uytterhoeven:
When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
the old symbols were kept, aiming to provide a seamless migration path
when running "make olddefconfig" or "make oldconfig".
However, the old compatibility symbols are no
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:20PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
> Compression Processor (FCPVD), Video Signal Processor (VSPD), and
> Display Unit (DU).
>
> There is
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:19PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> The DU block on the RZ/V2H(P) SoC is identical to the one found on the
> RZ/G2L SoC. However, it only supports the DSI interface, whereas the
> RZ/G2L supports both DSI an
Hi Prabhakar,
On Mon, May 12, 2025 at 07:23:21PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
I would write "5.803 MHz to 148.5 MHz" as ranges are usually expressed
in increasing order.
Reviewed-by: Laurent Pinchart
On Tue, May 06, 2025 at 11:00:58AM -0400, Alex Deucher wrote:
On Mon, May 5, 2025 at 7:16 PM Sasha Levin wrote:
From: Charlene Liu
[ Upstream commit 23ef388a84c72b0614a6c10f866ffeac7e807719 ]
[why]
failed due to cmdtable not created.
switch atombios cmdtable as default.
Reviewed-by: Alvin
On Tue, May 20, 2025 at 02:06:09PM +0100, Robin Murphy wrote:
> On 2025-05-20 12:31 pm, Will Deacon wrote:
> > On Thu, May 15, 2025 at 07:48:39AM -0700, Rob Clark wrote:
> > > On Thu, May 15, 2025 at 7:33 AM Will Deacon wrote:
> > > > On Wed, May 14, 2025 at 10:53:19AM -0700, Rob Clark wrote:
> >
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:22PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Simplify the high-speed clock frequency (HSFREQ) calculation by removing
> the redundant multiplication and division by 8. The updated equation:
>
> hsfreq = (mode->c
On Tue, May 06, 2025 at 11:02:34AM -0400, Alex Deucher wrote:
On Mon, May 5, 2025 at 7:04 PM Sasha Levin wrote:
From: Alex Deucher
[ Upstream commit 2ed83f2cc41e8f7ced1c0610ec2b0821c5522ed5 ]
Use the value pulled from the vbios just like newer chips.
Reviewed-by: Harry Wentland
Signed-off
On Tue, May 06, 2025 at 11:05:15AM -0400, Alex Deucher wrote:
On Mon, May 5, 2025 at 6:24 PM Sasha Levin wrote:
From: Alexandre Demers
[ Upstream commit ab23db6d08efdda5d13d01a66c593d0e57f8917f ]
DCE6 was missing soft reset, but it was easily identifiable under radeon.
This should be it, pr
Thomas Zimmermann writes:
> Hi
>
> Am 20.05.25 um 15:09 schrieb Geert Uytterhoeven:
>> Hi Thomas,
>>
>> On Tue, 20 May 2025 at 15:04, Thomas Zimmermann wrote:
>>> Am 20.05.25 um 14:40 schrieb Geert Uytterhoeven:
When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
t
Hi,
On Tue, May 20, 2025 at 5:43 AM wrote:
>
> From: Ernest Van Hoecke
>
> AUO G156HAN03.0 EDID:
>
> 00 ff ff ff ff ff ff 00 06 af ed 30 00 00 00 00
> 1a 1c 01 04 a5 22 13 78 02 05 b5 94 59 59 92 28
> 1d 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
> 01 01 01 01 01 01 78 37 80 b4 70 38 2e 40 6c
Hi Steven,
Thanks for the fix, I've tested it and it fixes the outstanding issue.
However, including the perfcnt sample buffer in the DebugFS GEMs file raises
the question of what
to do with its labelling, because it isn't exposed to UM through a handle, so
my previous assumption
about not need
Hi Thomas,
On Tue, 20 May 2025 at 15:04, Thomas Zimmermann wrote:
> Am 20.05.25 um 14:40 schrieb Geert Uytterhoeven:
> > When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
> > the old symbols were kept, aiming to provide a seamless migration path
> > when running "make oldde
Hi
Am 20.05.25 um 15:09 schrieb Geert Uytterhoeven:
Hi Thomas,
On Tue, 20 May 2025 at 15:04, Thomas Zimmermann wrote:
Am 20.05.25 um 14:40 schrieb Geert Uytterhoeven:
When moving the Sitronix DRM drivers and renaming their Kconfig symbols,
the old symbols were kept, aiming to provide a seaml
On Tue, May 20, 2025 at 12:23 AM Danilo Krummrich wrote:
>
> On Mon, May 19, 2025 at 10:51:24AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > See commit a414fe3a2129 ("drm/msm/gem: Drop obj lock in
> > msm_gem_free_object()") for justification.
>
> I asked for a proper commit message in v4.
On Tue, May 20, 2025 at 10:01:59AM +0100, Tvrtko Ursulin wrote:
Hi,
One question below in the context of the missing workarounds series I
am working on:
On 09/05/2025 17:12, Umesh Nerlige Ramappa wrote:
8><
+#define CONTEXT_ACTIVE 1ULL
+static void xe_lrc_setup_utilization(struct xe_lrc *
Hi Prabhakar,
On Mon, 12 May 2025 at 20:23, Prabhakar wrote:
> From: Lad Prabhakar
>
> Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
> VCLK rate instead of the mode clock. The relationship between HSCLK and
> VCLK is:
>
> vclk * bpp <= hsclk * 8 * lanes
>
> Retrieve
On Tue, May 20, 2025 at 09:43:42AM -0400, Joel Fernandes wrote:
> On 5/20/2025 5:30 AM, Danilo Krummrich wrote:
> > On Tue, May 20, 2025 at 03:55:06AM -0400, Joel Fernandes wrote:
> >> On 5/13/2025 1:19 PM, Danilo Krummrich wrote:
> >>> On Wed, May 07, 2025 at 10:52:43PM +0900, Alexandre Courbot wr
(+ Tvrtko, Rodrigo and Jani)
Quoting Krzysztof Niemiec (2025-05-19 18:34:14)
> Hi,
>
> This series introduces a way for applications to read local memory
> information via files in the sysfs. So far the only way to do this was
> via i915_query ioctl. This is slightly less handy than sysfs for
> e
On 5/20/2025 5:30 AM, Danilo Krummrich wrote:
> On Tue, May 20, 2025 at 03:55:06AM -0400, Joel Fernandes wrote:
>> On 5/13/2025 1:19 PM, Danilo Krummrich wrote:
>>> On Wed, May 07, 2025 at 10:52:43PM +0900, Alexandre Courbot wrote:
@@ -238,6 +239,8 @@ pub(crate) fn new(
On 2025-05-20 12:31 pm, Will Deacon wrote:
On Thu, May 15, 2025 at 07:48:39AM -0700, Rob Clark wrote:
On Thu, May 15, 2025 at 7:33 AM Will Deacon wrote:
On Wed, May 14, 2025 at 10:53:19AM -0700, Rob Clark wrote:
From: Rob Clark
In situations where mapping/unmapping sequence can be controll
On Thu, May 15, 2025 at 07:48:39AM -0700, Rob Clark wrote:
> On Thu, May 15, 2025 at 7:33 AM Will Deacon wrote:
> >
> > On Wed, May 14, 2025 at 10:53:19AM -0700, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > In situations where mapping/unmapping sequence can be controlled by
> > > userspace,
From: Konrad Dybcio
The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of
swizzling) is what we want on this platform (and others with a UBWC
1.0 encoder).
Fix it to make mesa happy (the hardware doesn't care about the 2 higher
bits, as they weren't consumed on this platform).
Re
Hi Prabhakar,
On Mon, May 12, 2025 at 07:23:23PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
> VCLK rate instead of the mode clock. The relationship between HSCLK and
> VCLK is:
>
> vclk * bpp <= hsclk * 8 * lanes
Hi Prabhakar,
Thank you for the patch.
On Mon, May 12, 2025 at 07:23:24PM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
> introduces a mechanism to pass SoC-specific information via OF data in the
> DSI driver. This
Update the header files describing the secure world ABI, both with and
without FF-A. The ABI is extended to deal with protected memory, but as
usual backward compatible.
Signed-off-by: Jens Wiklander
---
drivers/tee/optee/optee_ffa.h | 27 ---
drivers/tee/optee/optee_msg.h | 84 +
Implement DMA heap for protected DMA-buf allocation in the TEE
subsystem.
Restricted memory refers to memory buffers behind a hardware enforced
firewall. It is not accessible to the kernel during normal circumstances
but rather only accessible to certain hardware IPs or CPUs executing in
higher or
Add support in the OP-TEE backend driver dynamic protected memory
allocation with FF-A.
The protected memory pools for dynamically allocated protected memory
are instantiated when requested by user-space. This instantiation can
fail if OP-TEE doesn't support the requested use-case of protected
mem
Add support in the OP-TEE backend driver for dynamic protected memory
allocation using the SMC ABI.
Signed-off-by: Jens Wiklander
---
drivers/tee/optee/smc_abi.c | 102 ++--
1 file changed, 85 insertions(+), 17 deletions(-)
diff --git a/drivers/tee/optee/smc_abi.
From: Etienne Carriere
Add a userspace API to create a tee_shm object that refers to a dmabuf
reference.
Userspace registers the dmabuf file descriptor as in a tee_shm object.
The registration is completed with a tee_shm returned file descriptor.
Userspace is free to close the dmabuf file descr
Break out the memref handling into a separate helper function.
No change in behavior.
Signed-off-by: Jens Wiklander
Reviewed-by: Sumit Garg
---
drivers/tee/tee_core.c | 94 --
1 file changed, 54 insertions(+), 40 deletions(-)
diff --git a/drivers/tee/tee
Add support in the OP-TEE backend driver for protected memory
allocation. The support is limited to only the SMC ABI and for secure
video buffers.
OP-TEE is probed for the range of protected physical memory and a
memory pool allocator is initialized if OP-TEE have support for such
memory.
Signed-
Hi,
This patch set allocates the protected DMA-bufs from a DMA-heap
instantiated from the TEE subsystem.
The TEE subsystem handles the DMA-buf allocations since it is the TEE
(OP-TEE, AMD-TEE, TS-TEE, or perhaps a future QTEE) which sets up the
protection for the memory used for the DMA-bufs.
Th
Export the dma-buf heap functions declared in .
Signed-off-by: Jens Wiklander
---
drivers/dma-buf/dma-heap.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma-buf/dma-heap.c b/drivers/dma-buf/dma-heap.c
index 3cbe87d4a464..cdddf0e24dce 100644
--- a/drivers/dma-buf/dma-heap.c
+++
Add tee_shm_alloc_dma_mem() to allocate DMA memory. The memory is
represented by a tee_shm object using the new flag TEE_SHM_DMA_MEM to
identify it as DMA memory. The allocated memory will later be lent to
the TEE to be used as protected memory.
Signed-off-by: Jens Wiklander
---
drivers/tee/tee_
On 5/19/25 20:06, James wrote:
On Mon, May 5, 2025, at 9:02 AM, Alex Hung wrote:
Reviewed-by: Alex Hung
On 5/3/25 15:18, James Flowers wrote:
Adds kernel-doc for externally linked dc_stream_remove_writeback function.
Signed-off-by: James Flowers
---
V1 -> V2: Corrected checkpatch warni
On Tue, May 20, 2025 at 11:11:12AM -0400, Joel Fernandes wrote:
> On 5/20/2025 11:01 AM, Danilo Krummrich wrote:
>
> I made this change and it LGTM. Thanks! I did not do the '.0' though since I
> want to keep the readability, lets see in the next revision if that looks
> good.
I think readabilit
On Mon, 19 May 2025 10:51:23 -0700, Rob Clark wrote:
> Conversion to DRM GPU VA Manager[1], and adding support for Vulkan Sparse
> Memory[2] in the form of:
>
> 1. A new VM_BIND submitqueue type for executing VM MSM_SUBMIT_BO_OP_MAP/
>MAP_NULL/UNMAP commands
>
> 2. A new VM_BIND ioctl to allo
This patchset implements a request made by Xaver Hugl about wedge events:
"I'd really like to have the PID of the client that triggered the GPU
reset, so that we can kill it if multiple resets are triggered in a
row (or switch to software rendering if it's KWin itself) and show a
user-friendly not
Add a section about "Task information" for the wedge API.
Reviewed-by: Krzysztof Karas
Reviewed-by: Raag Jadav
Signed-off-by: André Almeida
---
v5:
- Change app to task in the text as well
v4:
- Change APP to TASK
v3:
- Change "app that caused ..." to "app involved ..."
- Clarify that devco
To notify userspace about which task (if any) made the device get in a
wedge state, make use of drm_wedge_task_info parameter, filling it with
the task PID and name.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +--
drivers/gpu/drm/amd/amdgpu/a
When a device get wedged, it might be caused by a guilty application.
For userspace, knowing which task was the cause can be useful for some
situations, like for implementing a policy, logs or for giving a chance
for the compositor to let the user know what task caused the problem.
This is an optio
On Tue, 20 May 2025 17:00:11 +0100
Conor Dooley wrote:
> On Tue, May 20, 2025 at 04:58:12PM +0100, Conor Dooley wrote:
> > On Tue, May 20, 2025 at 11:11:12AM -0400, Hugo Villeneuve wrote:
> > > From: Hugo Villeneuve
> > >
> > > Allow to inherit valid properties from the dsi-controller. This fix
Le 19/05/2025 à 17:34, Danilo Krummrich a écrit :
On Thu, Apr 24, 2025 at 10:38:15AM +0200, Pierre-Eric Pelloux-Prayer wrote:
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h
b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h
index f56e77e7f6d0..713df3516a17 100644
--- a/drivers/g
On 5/20/2025 11:36 AM, Danilo Krummrich wrote:
>>> If you want a helper type with Options while parsing that's totally fine,
>>> but
>>> the final result can clearly be without Options. For instance:
>>>
>>> struct Data {
>>>image: KVec,
>>> }
>>>
>>> impl Data {
>>>
Look mom, no generic soup!
Anyway - this is just the last of the cleanup stuff I ended up while
working on cleaning up the gem shmem patch series. It simplifies the use
of generics and also adds a type alias for some very long types
currently in use. Also, drop one unused constant I noticed.
Appl
One of the original intents with the gem bindings was that drivers could
specify additional gem implementations, in order to enable for driver
private gem objects. This wasn't really possible however, as up until now
our GEM bindings have always assumed that the only GEM object we would run
into wa
Just to reduce the clutter with the File<…> types in gem.rs.
Signed-off-by: Lyude Paul
---
V3:
* Rename ObjectFile to DriverFile
Signed-off-by: Lyude Paul
---
rust/kernel/drm/gem/mod.rs | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/rust/kernel/d
n Tue, May 20, 2025 at 12:54 PM Danilo Krummrich wrote:
>
> On Tue, May 20, 2025 at 09:07:05AM -0700, Rob Clark wrote:
> > On Tue, May 20, 2025 at 12:06 AM Danilo Krummrich wrote:
> > >
> > > On Thu, May 15, 2025 at 12:56:38PM -0700, Rob Clark wrote:
> > > > On Thu, May 15, 2025 at 11:56 AM Danil
From: Hugo Villeneuve
Add support for sending MIPI DSI command packets from the host to a
peripheral. This is required for panels that need configuration before
they accept video data.
Based on Renesas Linux kernel v5.10 repos [1].
Link: https://github.com/renesas-rz/rz_linux-cip.git
Cc: Biju D
From: Hugo Villeneuve
The default value of 1 will result in long read commands payload not being
saved to memory.
Fix by setting this value to the DMA buffer size.
Cc: Biju Das
Cc: Chris Brandt
Signed-off-by: Hugo Villeneuve
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 10 +
Functions for labelling UM-exposed an internal BOs are provided. An
example of the latter would be the Perfcnt sample buffer.
This commit is done in preparation of a following one that will allow
UM to set BO labels through a new ioctl().
Signed-off-by: Adrián Larumbe
Reviewed-by: Steven Price
Perfcnt samples buffer is not exposed to UM, but we would like to keep
a tag on it as a potential debug aid.
PRIME imported GEM buffers are UM exposed, but since the usual Panfrost
UM driver code path is not followed in their creation, they might remain
unlabelled for their entire lifetime, so a g
On Tue, May 20, 2025 at 01:13:26PM +0200, Krzysztof Kozlowski wrote:
> Driver unconditionally saves current state on first init in
> dsi_pll_10nm_init(), but does not save the VCO rate, only some of the
> divider registers. The state is then restored during probe/enable via
> msm_dsi_phy_enable()
On 2025-05-19 19:43, Simon Ser wrote:
> On Sunday, May 18th, 2025 at 00:32, Xaver Hugl wrote:
>
>>> We can always make the property mutable on drivers that support it in
>>
>>> the future, much like the zpos property. I think we should keep it
>>> immutable for now.
>>
>> Sure, but I don't see
From: Abhinav Kumar
[ Upstream commit aedf02e46eb549dac8db4821a6b9f0c6bf6e3990 ]
For cases where the crtc's connectors_changed was set without enable/active
getting toggled , there is an atomic_enable() call followed by an
atomic_disable() but without an atomic_mode_set().
This results in a NUL
From: Vinod Polimera
[ Upstream commit c0cd12a5d29fa36a8e2ebac7b8bec50c1a41fb57 ]
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewe
On Tue, May 20, 2025 at 12:00:53PM +0200, Maxime Ripard wrote:
> +Naming Convention
> +=
> +
> +A good heap name is a name that:
> +
> +- Is stable, and won't change from one version to the other;
> +
> +- Describes the memory region the heap will allocate from, and will
> + unique
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