> > +static void *pci_mmconfig_addr(u16 bdf, u32 addr)
> > +{
> > + if (!mmconfig)
> > + return NULL;
> > + return (void*)(mmconfig + ((u32)bdf << 12) + addr);
> > +}
> > +
> > void pci_config_writel(u16 bdf, u32 addr, u32 val)
> > {
> > - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
> > - outl(val, PORT_PCI_DATA);
> > + void *mmcfg = pci_mmconfig_addr(bdf, addr);
> > + if (mmcfg) {
> > + writel(mmcfg, val);
> > + } else {
> > + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
> > + outl(val, PORT_PCI_DATA);
> > + }
> > }
>
> The pci_config_writeX() functions are called from 16-bit mode and
> 32-big segment mode, so this doesn't look correct to me.
Oh. Wasn't aware of that.
> What device would call the pci_config_writeX() functions frequently
> enough that performance would matter?
I expect most vmexists come from PCI bar configuration in POST which
runs in 32bit mode. I think we can restrict this to 32bit mode without
loosing much.
cheers,
Gerd
>From efd637133232fc8beec3a2f8bb4af505192758d1 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <[email protected]>
Date: Fri, 20 Mar 2020 06:45:10 +0100
Subject: [PATCH] no mmconfig in 16bit mode
---
src/hw/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/hw/pci.c b/src/hw/pci.c
index 3b8f43cbe5dc..9ae57ff28707 100644
--- a/src/hw/pci.c
+++ b/src/hw/pci.c
@@ -18,6 +18,8 @@ static u32 mmconfig;
static void *pci_mmconfig_addr(u16 bdf, u32 addr)
{
+ if (MODESEGMENT)
+ return NULL;
if (!mmconfig)
return NULL;
return (void*)(mmconfig + ((u32)bdf << 12) + addr);
--
2.18.2
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