From: "Ronald G. Minnich" <[email protected]>
Date: Thu, 24 May 2012 11:27:26 -0700
Serial port detection in SeaBIOS tests for bit 2 in the IER. That bit is
never set, and SeaBIOS mistakenly reports 0 serial ports. As it happens,
just testing for IER to be not-all-ones is good enough.
This happens on all systems where the AP serial port uses the Blizzard
EC (Ivy Bridge, Haswell). Does not affect Bay Trail, since we use the
native Intel serial port.
It’s a hardware limitation of which registers the Blizzard COMx port
implementation provides. Nothing we can do in EC software.
BUG=chrome-os-partner:9946
TEST=build SeaBIOS with serial port enabled, and note that SeaBIOS
says
init serial
Found 1 serial ports
BRANCH=none
Signed-off-by: Ronald G. Minnich <[email protected]>
Change-Id: I6bee73788ca6533091d85e54d05b37a564f910a7
Reviewed-on: https://chromium-review.googlesource.com/184421
Reviewed-by: Stefan Reinauer <[email protected]>
Commit-Queue: Stefan Reinauer <[email protected]>
Tested-by: Stefan Reinauer <[email protected]>
Reviewed-on: https://chromium-review.googlesource.com/227500
Signed-off-by: Paul Menzel <[email protected]>
---
src/serial.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/serial.c b/src/serial.c
index 88349c8..e67ac77 100644
--- a/src/serial.c
+++ b/src/serial.c
@@ -26,10 +26,12 @@ detect_serial(u16 port, u8 timeout, u8 count)
return 0;
outb(0x02, port+SEROFF_IER);
u8 ier = inb(port+SEROFF_IER);
- if (ier != 0x02)
+ dprintf(8, "IER is 0x%02x (Expected 0x02 or 0x00)\n", ier);
+ if (ier != 0x02 && ier != 0)
return 0;
u8 iir = inb(port+SEROFF_IIR);
- if ((iir & 0x3f) != 0x02)
+ dprintf(8, "IIR is 0x%02x (Expected != 0x3f)\n", iir & 0x3f);
+ if ((iir & 0x3f) == 0x3f)
return 0;
outb(0x00, port+SEROFF_IER);
--
2.25.1
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