On Thu, Aug 09, 2018 at 07:44:22AM +0800, Zihan Yang wrote: > Kevin O'Connor <[email protected]> 于2018年8月8日周三 下午10:14写道： > > On Thu, Aug 02, 2018 at 10:39:13AM +0800, Zihan Yang wrote: > > > NOTE: This patch set is still ongoing and does not fully function > > > as its goal. But it involves some API changes, therefore I post them for > > > comments before moving on to make sure I'm on the right path. > > > > > > The corresponding qemu part can be found at > > > https://gitlab.com/WhoisZihan/qemu-pci-domain/tree/master/qemu > > > I will submit it to qemu list later. > > > > > > Currently seabios assumes there is only one pci domain(0), and almost > > > everything operates on pci domain 0 by default. This patch aims to add > > > multiple pci domain support for pci_device, while reserve the original > > > API for compatibility. > > > > Thanks. I understand the desire to support multiple PCI domains in > > QEMU and the guest OS. However, what is the high level reason for > > wanting the BIOS to be able to interact with the secondary PCI > > domains? > > The pxb-pcie host bus is put into a separated domain, so are the devices > under the pxb host bus. I think we should also initialize busses in other > domains and probe those devices during bios initialization. But currently > qemu only binds port 0xcf8 and 0xcfc to q35 host's conf_mem and data_mem, > if we want to read the config space of pxb host, we should use another port. > I use port range 0x1000 and 0x1004 for a temporary workaround because they > seem to be 'free' now.
The patchset is quite large and touches a large amount of code in different parts of SeaBIOS. I'd like to understand the high-level, user-visible, reason for making the change. What important capabilities will a user be unable to accomplish if we don't make this change? As far as I know, there is no standard for accessing PCI besides the main one at cf8/cfc - so I'm not sure there is a good solution to this problem. Perhaps it would be easier for users to always put their boot devices on the main PCI. Thanks, -Kevin _______________________________________________ SeaBIOS mailing list [email protected] https://mail.coreboot.org/mailman/listinfo/seabios
