> Ah, yes. Level-triggered interrupts. So I guess I'll just drop support
for 2) for the z80 and z180 backends.
We can keep it for the tlcs90, r2k and r3ka, which use edge-triggered
interrupts. Anyone know about gbz80?
No number 2 is correct for the z80 in im2 mode with hardware acknowledge and
hardware interrupt priority. Old computers like msx did not take advantage of
im2 mode so they tended to have simple interrupt schemes involving polling and
level interrupts.
>1) non-interruptible isr (can be interrupted by nmi only):
>void i1(void) __interrupt
push
...
pop
ei
reti
>2) interruptible isr (can be interrupted by any interupt)
>void i2(void) __critical __interrupt(0)
ei
push
...
pop
reti
This is suitable for daisy chain im2 mode where interrupt priority and
acknowledge is done in hardware. All of Zilog's peripherals conform to this
but quite often implementations do not take advantage of it.
>3) nmi handler (can be interrupted by nmi only)
>void i3(void) __critical __interrupt
push
..
pop
retn
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