Yesterday, we discovered the following while developing the STM8 port with Philipp (we're testing on real hardware).
1) addw SP, #XX takes signed value and costs 1 cycle 2) sub SP, #XX takes unsigned value and costs 1 cycle I'm just wondering if it can be met with ucsim. P.S. chip used: stm8l152c6t6 ------------------------------------------------------------------------------ Precog is a next-generation analytics platform capable of advanced analytics on semi-structured data. The platform includes APIs for building apps and a phenomenal toolset for data science. Developers can use our toolset for easy data analysis & visualization. Get a free account! http://www2.precog.com/precogplatform/slashdotnewsletter _______________________________________________ Sdcc-user mailing list Sdcc-user@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sdcc-user
