Hi,

> This would be good for a new type: __sfr16_t  ---  "t" -> timer
>
> Perhaps even these will: __sfr16_be  ---  "be" -> big-endian
>                                         __sfr16_le  ---  "le" -> little-endian
>
> Otherwise, I now updated the PIC16 branch (device and include files). From 
> now on use the __ sfr16
> type. Due to the above to TMRx registers, no sfr16.

What are the consequences to code generation functions if you
introduce a new type / new types in order to guarantee LSB first/MSB
first access? Are sfr/__sfr16 data first read via some volatile read
fuction (iCode?), then processed, and then written back via some
volatile write function (iCode?)? Otherwise, probably all code
generation functions need to be revised to guarantee proper behaviour
[1].
Do you plan to introduce all four probably variations of 16-bit SFRs
(read order LSB or MSB first vs. write order LSB or MSB first)?

I am not even sure if all (PIC14/PIC16) functions properly honor
volatile -- they might read/assign their operands multiple times,
possibly even depending on runtime conditions.

Are we sure not to introduce additional, subtle bugs here?

Do not get me wrong: I'd like direct support for multi-bype SFRs, I
just want to avoid special cases throughout the backend.

> __at(0x0FC3) __sfr ADRES;
>
> __at(0x0FC3) __sfr ADRESL;
> __at(0x0FC3) __sfr16 ADRESw;
>
> __at(0x0FC4) __sfr ADRESH;

Do gputils (gplink) allow this? We end up with ADRESL and ADRESw
occupying 0xFC3 as well as ADRSH and ADRESw occupying 0xFC4. *Should*
the linker allow this?!?

Best regards
Raphael


[1]: I assume that SFRs should be usable in statements such as

ADRESw += 0x0101;

even though as user one *should* probably use

unsigned temp = ADRESw;
temp += 0x0101;
ADRESw = temp;

which would then only require assignments from / to SFR types to be
handled correctly.

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