my lab has modify the STC 51 architecture. Generally have the following two aspects: 1.The original six pipeline instead of two pipeline.Aiming at accelerate the 8051 processing The first machine cycle, read the instruction and functional decode; The two machine cycle,operating instructions and write data to relevant registers 2.Increase an extern flash chip,to expand the ROM spatial capacity In order to coordinate the amendment,we have added a few instructions to control the flash, at the same time, we have added some new registers to latch the operation codes of flash Basically only these! So,what should I do? Thanks! Donald
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