While I'm here attached is a modified copy of the w7100.h file in
SDCC. I sent a copy to the author some time back but haven't heard anything.
I don't quarantee this is entirely correct, but it at least builds and runs
on the W7100.
Peter Van Epp
/*-------------------------------------------------------------------------
Register Declarations for WIZnet's W7100
(Based on Internet Embedded MCU W7100 Datasheet Version 0.9 Beta)
Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (December 2009)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option); any later version
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Feb 2010 - Peter Van Epp - Corrected a typo in a #define
Jan 2010 - Peter Van Epp - reformatted to match the example w7100.h file
from the Wiznet site, added some comments and corrected a
couple of bugs.
-------------------------------------------------------------------------*/
#ifndef REG_W7100_H
#define REG_W7100_H
#include <compiler.h>
SFR(P0, 0x80); /* GPIO port 0 */
SBIT(P0_0, 0x80, 0);
SBIT(P0_1, 0x80, 1);
SBIT(P0_2, 0x80, 2);
SBIT(P0_3, 0x80, 3);
SBIT(P0_4, 0x80, 4);
SBIT(P0_5, 0x80, 5);
SBIT(P0_6, 0x80, 6);
SBIT(P0_7, 0x80, 7);
SFR(SP, 0x81); /* Stack pointer */
SFR16(DPTR0, 0x82); /* Data Pointer Register 0 */
SFR(DPL0, 0x82); /* Data Pointer Register 0 low */
SFR(DPH0, 0x83); /* Data Pointer Register 0 high */
SFR16(DPTR1, 0x84); /* Data Pointer Register 1 */
SFR(DPL1, 0x84); /* Data Pointer Register 1 low */
SFR(DPH1, 0x85); /* Data Pointer Register 1 high */
SFR(DPS, 0x86); /* Data Pointer Select Register */
#define SEL 0x01 /* DPTR register select */
#define TSL 0x20 /* Toggle select enable */
#define ID0 0x40 /* DPTR0, DPTR1 Operations bit 0 */
#define ID1 0x80 /* DPTR1, DPTR1 Operations bit 1 */
SFR(PCON, 0x87); /* Power Configuration Register */
#define PWE 0x10 /* Program Code Memory Write Enable Bit */
#define SMOD1 0x40 /* unimplemented? */
#define SMOD0 0x80 /* Baud rate select bit */
/* 1 clock from timer1 ovflow */
/* 0 clock from timer1 ovflow / 2 */
SFR(TCON, 0x88); /* Timer0, 1 configuration register. */
SBIT(IT0, 0x88, 0); /* INT0 mode: level (at 0) edge (at 1) */
SBIT(IE0, 0x88, 1); /* INT0 interrupt flag. */
SBIT(IT1, 0x88, 2); /* INT1 mode: level (at 0)/edge (at 1) */
SBIT(IE1, 0x88, 3); /* INT1 interrupt flag. */
SBIT(TR0, 0x88, 4); /* Timer 0 run control bit */
/* 0: Disabled. */
/* 1: Enabled. */
SBIT(TF0, 0x88, 5); /* Timer 0 interrupt (overflow) flag. */
SBIT(TR1, 0x88, 6); /* Timer 1 run control bit */
/* 0: Disabled. */
/* 1: Enabled. */
SBIT(TF1, 0x88, 7); /* Timer 1 interrupt (overflow) flag. */
SFR(TMOD, 0x89); /* Timer 0 and 1 mode control register. */
#define T0_M0 0x01 /* M1 M0 Mode Description */
#define T0_M1 0x02 /* 0 0 0 8 bit timer, / 32 prescaler */
/* 0 1 1 16 bit timer thx and tlx */
/* 1 0 2 tlx 8bit counter reloads tlh */
/* 1 1 3 tl0 8 bit th0 8bit t1 frozen */
#define T0_CT 0x04 /* 0 - timer 1 - counter */
#define T0_GATE 0x08 /* 0 - TRx enables 1 gate pin enables */
#define T1_M0 0x10 /* Same as for timer 0 above */
#define T1_M1 0x20
#define T1_CT 0x40
#define T1_GATE 0x80
SFR(TL0, 0x8A); /* Counter register of timer 0 low. */
SFR(TL1, 0x8B); /* Counter register of timer 1 low. */
SFR(TH0, 0x8C); /* Counter register of timer 0 high. */
SFR(TH1, 0x8D); /* Counter register of timer 1 high. */
SFR(CKCON, 0x8E); /* Clock Control Register */
#define MD0 0x01 /* Memory wait stretch bit 0 */
#define MD1 0x02 /* Memory wait stretch bit 1 */
#define MD2 0x04 /* Memory wait stretch bit 2 */
/* currently unused */
#define WD0 0x40 /* Watchdog interval bit 0 */
#define WD1 0x80 /* Watchdog interval bit 1 */
SFR(P1, 0x90); /* GPIO port 1 */
SBIT(P1_0, 0x90, 0);
SBIT(P1_1, 0x90, 1);
SBIT(P1_2, 0x90, 2);
SBIT(P1_3, 0x90, 3);
SBIT(P1_4, 0x90, 4);
SBIT(P1_5, 0x90, 5);
SBIT(P1_6, 0x90, 6);
SBIT(P1_7, 0x90, 7);
SFR(EIF, 0x91); /* Extended Interrupt Flag Register. */
#define INT2F 0x01 /* INT2 interrupt flag. */
/* Must be cleared by software. */
#define INT3F 0x02 /* INT3 interrupt flag. */
/* Must be cleared by software. */
#define INT4F 0x04 /* Must be set to '0'. */
#define INT5F 0x08 /* TCPIPCore Interrupt flag. */
/* Must be cleared by software. */
SFR(WTST, 0x92); /* Program Code Memory Wait States */
SBIT(WTST0, 0x92, 0); /* Wait States Register bit 0 */
SBIT(WTST1, 0x92, 1); /* Wait States Register bit 1 */
SBIT(WTST2, 0x92, 2); /* Wait States Register bit 2 */
SFR(DPX0, 0x93); /* Data Pointer Extended Register low */
SFR(DPX1, 0x95); /* Data Pointer Extended Register high */
SFR(SCON, 0x98); /* UART Configuration Register. */
SBIT(RI, 0x98, 0); /* UART receiver interrupt flag. */
SBIT(TI, 0x98, 1); /* UART transmitter interrupt flag. */
SBIT(RB8, 0x98, 2); /* The 9th received data bit in */
/* Modes 2 and 3. */
SBIT(TB8, 0x98, 3); /* The 9th transmitted data bit in */
/* Modes 2 and 3. */
SBIT(REN, 0x98, 4); /* Enable/Disable serial receive. */
SBIT(SM2, 0x98, 5); /* Enable a multiprocessor sync */
/* communication feature. */
SBIT(SM1, 0x98, 6); /* SM0,SM1 set baud rate: */
SBIT(SM0, 0x98, 7); /* 0 0 - sync shift register baud: fosc/12 */
/* 0 1 - 8 bit uart baud: timer1/2 overflow */
/* 1 0 - 9 bit uart */
/* SMOD = 1 bsud: fosc/32 */
/* SMOD = 0 bsud: fosc/64 */
/* 1 1 - 9 bit uart baud: timer1/2 overflow */
SFR(SBUF, 0x99); /* UART Buffer Register. */
SFR(P2, 0xA0); /* GPIO port 2 */
SBIT(P2_0, 0xA0, 0);
SBIT(P2_1, 0xA0, 1);
SBIT(P2_2, 0xA0, 2);
SBIT(P2_3, 0xA0, 3);
SBIT(P2_4, 0xA0, 4);
SBIT(P2_5, 0xA0, 5);
SBIT(P2_6, 0xA0, 6);
SBIT(P2_7, 0xA0, 7);
SFR(IE, 0xA8); /* Interrupt Enable Register. */
SBIT(EX0, 0xA8, 0); /* Enable INT0 interrupt. */
SBIT(ET0, 0xA8, 1); /* Enable Timer0 interrupt. */
SBIT(EX1, 0xA8, 2); /* Enable INT1 interrupt. */
SBIT(ET1, 0xA8, 3); /* Enable Timer1 interrupt. */
SBIT(ES, 0xA8, 4); /* Enable UART interrupt. */
SBIT(ET2, 0xA8, 5); /* Enable Timer2 interrupt. */
SBIT(EA, 0xA8, 7); /* Enable global interrupt. */
SFR(P3, 0xB0); /* GPIO port 3 */
SBIT(P3_0, 0xB0, 0);
SBIT(P3_1, 0xB0, 1);
SBIT(P3_2, 0xB0, 2);
SBIT(P3_3, 0xB0, 3);
SBIT(P3_4, 0xB0, 4);
SBIT(P3_5, 0xB0, 5);
SBIT(P3_6, 0xB0, 6);
SBIT(P3_7, 0xB0, 7);
SFR(IP, 0xB8); /* Interrupt Priority Register. */
SBIT(PX0, 0xB8, 0); /* INT0 priority level control. */
SBIT(PT0, 0xB8, 1); /* Timer0 priority level control. */
SBIT(PX1, 0xB8, 2); /* INT1 priority level control. */
SBIT(PT1, 0xB8, 3); /* Timer1 priority level control. */
SBIT(PS, 0xB8, 4); /* UART priority level control. */
SBIT(PT2, 0xB8, 5); /* Timer2 priority level control. */
SFR(TA, 0xC7); /* Timed Access Register. */
/* write 0xAA followd by 0X55 to TA */
/* then write WDCON on the next cycle */
SFR(T2CON, 0xC8); /* Timer 2 Configuration Register. */
SBIT(CPRL2, 0xC8, 0); /* Capture reload 0: auto reload on overflow */
/* if EXEN2 = 0 or RCLK or TCLK is set */
/* if EXEN2 is 1 and RCLK and TCLK unset */
/* then reload on the falling edge of T2EX */
SBIT(CT2, 0xC8, 1); /* Timer/Counter select. */
SBIT(TR2, 0xC8, 2); /* Start/Stop Timer2. */
SBIT(EXEN2, 0xC8, 3); /* Enable T2EX pin functionality. */
SBIT(TCLK, 0xC8, 4); /* Transmit clock enable. */
SBIT(RCLK, 0xC8, 5); /* Receive clock enable. */
SBIT(EXF2, 0xC8, 6); /* Indicates a Falling edge in the */
/* T2EX pin when EXEN2=1. */
SBIT(TF2, 0xC8, 7); /* Timer2 overflow flag. */
SFR(RLDL, 0xCA); /* Capture Registers of Timer 2 low. */
SFR(RLDH, 0xCB); /* Capture Registers of Timer 2 high. */
SFR(TL2, 0xCC); /* Counter Register of Timer 2 low. */
SFR(TH2, 0xCD); /* Counter Register of Timer 2 high. */
SFR(PSW, 0xD0); /* Program Status Word Register. */
SBIT(P, 0xD0, 0); /* Parity flag. */
SBIT(F1, 0xD0, 1); /* General purpose flag 1. */
SBIT(OV, 0xD0, 2); /* Overflow flag. */
SBIT(RS0, 0xD0, 3); /* Register bank select bit 0. */
SBIT(RS1, 0xD0, 4); /* Register bank select bit 1. */
SBIT(F0, 0xD0, 5); /* General purpose flag 0. */
SBIT(AC, 0xD0, 6); /* Auxiliary carry. */
SBIT(CY, 0xD0, 7); /* Carry flag. */
SFR(WDCON, 0xD8); /* Watchdog Control Register */
SBIT(RWT, 0xD8, 0); /* Reset the Watchdog Timer. */
SBIT(EWT, 0xD8, 1); /* Enable the Watchdog Timer reset. */
SBIT(WTRF, 0xD8, 2); /* Watchdog Timer reset Flag. */
SBIT(WDIF, 0xD8, 3); /* Watchdog Interrupt Flag. */
SFR(ACC, 0xE0); /* Accumulator */
SBIT(ACC_0, 0xE0, 0);
SBIT(ACC_1, 0xE0, 1);
SBIT(ACC_2, 0xE0, 2);
SBIT(ACC_3, 0xE0, 3);
SBIT(ACC_4, 0xE0, 4);
SBIT(ACC_5, 0xE0, 5);
SBIT(ACC_6, 0xE0, 6);
SBIT(ACC_7, 0xE0, 7);
SFR(EIE, 0xE8); /* Extended Interrupt Enable Register. */
SBIT(EINT2, 0xE8, 0); /* Enable INT2 Interrupt. */
SBIT(EINT3, 0xE8, 1); /* Enable INT3 Interrupt. */
SBIT(EINT4, 0xE8, 2); /* Must be set to '0'. */
SBIT(EINT5, 0xE8, 3); /* Enable TCPIPCore Interrupt. */
SBIT(EWDI, 0xE8, 4); /* Enable WATCHDOG Interrupt. */
SFR(MXAX, 0xEA); /* Data Pointer Extended Register */
SFR(B, 0xF0); /* Register B */
SBIT(B_0, 0xF0, 0);
SBIT(B_1, 0xF0, 1);
SBIT(B_2, 0xF0, 2);
SBIT(B_3, 0xF0, 3);
SBIT(B_4, 0xF0, 4);
SBIT(B_5, 0xF0, 5);
SBIT(B_6, 0xF0, 6);
SBIT(B_7, 0xF0, 7);
SFR(ISPID, 0xF1); /* ID Register for ISP. */
SFR16(ISPADDR16, 0xF2); /* 16bit Address Register for ISP */
SFR(ISPDATA, 0xF4); /* Data Register for ISP. */
SFR(CKCBK, 0xF5); /* CKCON Backup Register. */
SFR(DPX0BK, 0xF6); /* DPX0 Backup Register. */
SFR(DPX1BK, 0xF7); /* DPX1 Backup Register. */
SFR(EIP, 0xF8); /* Extended Interrupt Priority Register */
SBIT(PINT2, 0xF8, 0); /* INT2 priority level control. */
SBIT(PINT3, 0xF8, 1); /* INT3 priority level control. */
SBIT(PINT4, 0xF8, 2); /* Must be set to '0'. */
SBIT(PINT5, 0xF8, 3); /* TCPIPCore Interrupt priority level */
SBIT(PWDI, 0xF8, 4); /* WATCHDOG priority level control. */
SFR(DPSBK, 0xF9); /* DPX Backup Register. */
/* WARNING: the following six definitions are not well documented */
SFR16(RAMBA16, 0xFA); /* RAM Base Address Register. */
SFR(RAMBA16L, 0xFA); /* RAM base Address Register low byte */
SFR(RAMBA16H, 0xFB); /* RAM base Address Register high byte */
SFR16(RAMEA16, 0xFC); /* RAM End Address Register. */
SFR(RAMEA16L, 0xFC); /* RAM End Address Register low byte */
SFR(RAMEA16H, 0xFD); /* RAM End Address Register high byte */
SFR(WCONF, 0xFF); /* W7100 Configuration Register. */
/* (needs to be done as bits, can't be */
/* SBIT) */
#define BE 0x01 /* Boot Enable */
/* 0 : Apps Running). Read only. */
/* 1 : Boot Running */
#define FB 0x02 /* FLASH Busy Flag for ISP. Read only. */
#define F64EN 0x04 /* Always '0'. Read only. */
#define ISPEN 0x40 /* 0 : Enable ISP in Boot built in W7100 */
/* 1 : Disable. */
#define RB 0x80 /* 0 : No Reboot */
/* 1 : Reboot after the ISP done. */
/* As of the latest snapshot release the following keywords are */
/* depreciated in SDCC so modify them to their new values to avoid the */
/* warnings. The other compilers presumably still use the old names */
/* which is why to not change the code instead. */
#define xdata __xdata
#define interrupt __interrupt
#define code __code
#define bit __bit
#define sbit __sbit
#define using __using
#endif /*REG_W7100_H*/
------------------------------------------------------------------------------
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