I even went as far as replacing the PIO chips with some new ones, so convinced
was I that I was doing things correctly. I wasn't, of course.
The designers of this circuit (I'm doing a reverse engineering job) arranged
the C/'D and A/'B lines the opposite way around to Zilog's suggestion of
connecting them to A0 and A1, so in effect I was addressing the ports
entirely wrongly. Only when I came to verify my assumptions with some simple
continuity testing did it become clear where I had made my blunder. A quick
change to the #define macros for the ports and everything sprung into life
exactly as it should after a recompile and blowing a new EPROM.
I've spent four days wrestling with this problem, including looking at the
timing of M1 to make sure that it wasn't continually resetting the PIO (M1
without 'RD or 'IOREQ causes a reset, apparently) - all a complete waste of
time in retrospect. Now maybe I'll get some decent sleep, I've been so
preoccupied!
Hey-ho.
On Saturday 28 February 2009 23:37:20 Jacques Pelletier wrote:
<snip>
> > Can anyone suggest where I might be going wrong? The generated assembly
> > code shows in0 and out0 instructions, but they still address the correct
> > port address so I don't really see a problem with that, and the same
> > principle is used for the Zilog CTC and that works fine.
> >
> > I'm completely baffled. Any suggestions would be welcome.
>
> You should add M1 to your logic analyser; the Z80 PIO chip generates its
> own write signal. Here's the equation from the specs of the PIO:
> /WR = RD . /CE . /IORQ . /M1 (I'm not sure if my old Z80 book is right)
>
> Good luck!
>
> JP
>
<snip>
--
Richard.
PGP Key-id: 0x5AB3D350
It's not enough to be Hungarian; you must have talent too.
-- Alexander Korda
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