Hi Folks,
Somewhat tangential to the hullabaloo going on at the moment about
documentation, I'm bound to say that Zilog's documentation about the Z180 MMU
is perplexing for me at least. For comparison's sake, I looked-up the Hitachi
64180 documentation and that was no more enlightening.
I understand the MMU rudiments in that the various registers represent 4K
offsets which compute an eventual physical address in a 20-bit (1MB) space;
but what I cannot get a handle upon is relative to what registers these
various offsets apply.
Perhaps the right place to start with this question is to lay on the table
what the physical hardware layout is, what my ideal software aims are and
then take it from there?
I have a ROM memory space from 00000-07FFF (physical) and RAM space from
08000-17FFF (physical). In other words, this is 32KB of ROM and 64KB RAM.
What I would ideally like is for op-code fetches and immediate mode data
fetches to be from ROM, and everything else from RAM, including the stack
which would be initially set at 17FFF (physical), growing down the RAM area,
and static variables at 08000 (physical) growing up the RAM area.
Can anyone set me straight on this, especially bearing in mind that SDCC
doesn't know anything about the 20-bit address space or the MMU and as far as
it is concerned there's only a 64K address space, as per the original Z80.
Many thanks in anticipation!
--
Richard.
PGP Key-id: 0x5AB3D350
A rock pile ceases to be a rock pile the moment a single man
contemplates it, bearing within him the image of a cathedral.
-- Antoine de Saint-Exupery
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