On Sunday 13 July 2008, [EMAIL PROTECTED] wrote: > which version of sdcc are you using? In my version (2.8.0) TMR2ON is > defined in the T2CON_bits struct. Anyway i just saw the TMR2ON is set to > T2CON_bits.TMR2ON with a #define. >
2.8.2 > As a workaround you could use the pwm initialization example written in > assembler from DS33023 > (http://ww1.microchip.com/downloads/en/DeviceDoc/33023a.pdf Page 216) to > see whether this is an sdcc specific problem. > Be aware that they assume the pwm output is on Port C! I have had some sucess by changing the device to the 16f88. I have a suspicion that there may be a problem with the header files for the 16f628a*. I copied the example you suggested and modified it to suit the 16f628 and it still would not work. Look at my new setup routine - the lines CLRF CCP1CON and CLRF TMR2 cause gpsim to cough giving the following error: (* my assumption - I'm not too knowledgable here) **gpsim> attempt write to invalid file register address 0x117, value 0x0 could not decode trace type: 0x0 0x0000000000000177 p16f628 0x00A9 0x20C8 call 0x00c8 0x0000000000000178 p16f628 0x00C8 0x0197 clrf _CCP1CON_bits Invalid Trace entry: 0x0 Wrote: 0x00DC to _STATUS_bits(0x0003) was 0x00DC Commenting out the two assembly lines CLRF CCP1CON and CLRF TMR2 and using the lines of C stopped gpsim throwing the wobbly. However, PWM not working. Change the device to 16f88 and make a few adjustments (to another part of the programme) due to a clash of pin designations and all looks well. void pwm_setup(void) { _asm ;#define STATUS 0x03 CLRF CCP1CON ; CCP Module is off CLRF TMR2 ; Clear Timer2 ;clrf 0x11 ; timer 2 is 0x11 _endasm; CCP1CON = 0; TMR2 = 0; _asm MOVLW 0x7F ; MOVWF PR2 ; MOVLW 0x1F ; MOVWF CCPR1L ; Duty Cycle is 25% of PWM Period CLRF INTCON ; Disable interrupts and clear T0IF ;BSF STATUS, RP0 ; Bank1 bsf STATUS,5 ;BCF TRISC, PWM1 ; Make pin output bcf TRISB,3 CLRF PIE1 ; Disable peripheral interrupts ;BCF STATUS, RP0 ; Bank0 bcf STATUS,5 CLRF PIR1 ; Clear peripheral interrupts Flags MOVLW 0x2C ; PWM mode, 2 LSbs of Duty cycle = 10 MOVWF CCP1CON ; ;BSF T2CON, TMR2ON ; Timer2 starts to increment bsf T2CON,2 ; ; The CCP1 interrupt is disabled, ; do polling on the TMR2 Interrupt flag bit ; ;PWM_Period_Match ; BTFSS PIR1, TMR2IF ; GOTO PWM_Period_Match ; ; Update this PWM period and the following PWM Duty cycle ; ; BCF PIR1, TMR2IF _endasm; } -- Peter Chant http://www.petezilla.co.uk ------------------------------------------------------------------------- Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 _______________________________________________ Sdcc-user mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sdcc-user
