On Fri, Dec 11, 2009 at 11:03 AM, Dag Sverre Seljebotn
<da...@student.matnat.uio.no> wrote:
> I just tracked down a problem down to a Sage ATLAS miscompile on my CPU;
> disabling SSE3 did the trick. How do I proceed to fix it permanently and

Did you install a binary or build from source.

> submit a patch? My /proc/cpuinfo is below.
>
> The strange thing is that /proc/cpuinfo doesn't contain SSE3, but still
> ATLAS didn't crash, in fact it would only a seldom time randomly produce
> wrong results (NaN in complex double matrix multiplication) when I had
> earlier produced a plot...that kind of thing...reproducable with 80%
> rate perhaps, not deterministic. Is there a chance SSE3 is buggy and
> disabled by the Linux kernel, or similar?
>
> The end-result is pretty nasty so if nobody knows an answer I should
> perhaps take it to the ATLAS list...
>
> The SAGE_FAT_BINARYfix did the trick. How do I proceed to fix it
> permanently and submit a patch? My /proc/cpuinfo is below.
>
> Also, "uname -p" returns "unknown" on my system, causing SAGE_FAT_BINARY
> to fail (so I had to hack the spkg). Would it be ok to replace this with
> (or fall back to) "uname -m"?
>
> $ uname -p
> unknown
> $ uname -m
> x86_64
> $ uname -i
> unknown
> $ uname -a
> Linux corcaroli.uio.no 2.6.18-128.7.1.el5 #1 SMP Wed Aug 19 04:00:49 EDT
> 2009 x86_64 GNU/Linux
>
> /proc/cpuinfo:
> processor       : 0
> vendor_id       : GenuineIntel
> cpu family      : 15
> model           : 4
> model name      :                   Intel(R) Xeon(TM) CPU 3.20GHz
> stepping        : 3
> cpu MHz         : 3200.218
> cache size      : 2048 KB
> physical id     : 0
> siblings        : 2
> core id         : 0
> cpu cores       : 1
> apicid          : 0
> fpu             : yes
> fpu_exception   : yes
> cpuid level     : 5
> wp              : yes
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall
> nx lm constant_tsc pni monitor ds_cpl cid cx16 xtpr
> bogomips        : 6404.61
> clflush size    : 64
> cache_alignment : 128
> address sizes   : 36 bits physical, 48 bits virtual
> power management:
>
> (same repeated for 3 more cores)
>
> Dag Sverre
>
> --
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-- 
William Stein
Associate Professor of Mathematics
University of Washington
http://wstein.org

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