https://git.reactos.org/?p=reactos.git;a=commitdiff;h=f420f2e5dfe824c771da4583559249b8bee2092c
commit f420f2e5dfe824c771da4583559249b8bee2092c Author: Stanislav Motylkov <[email protected]> AuthorDate: Wed Aug 26 02:06:19 2020 +0300 Commit: Stanislav Motylkov <[email protected]> CommitDate: Wed Aug 26 02:06:19 2020 +0300 [XBOX] Move SuperIO definitions and helpers into header file CORE-16216 --- boot/freeldr/freeldr/arch/i386/xbox/machxbox.c | 26 ++-- boot/freeldr/freeldr/include/arch/i386/machxbox.h | 15 --- sdk/include/reactos/drivers/xbox/superio.h | 147 ++++++++++++++++++++++ 3 files changed, 156 insertions(+), 32 deletions(-) diff --git a/boot/freeldr/freeldr/arch/i386/xbox/machxbox.c b/boot/freeldr/freeldr/arch/i386/xbox/machxbox.c index 6f54188e3f0..1551c664c29 100644 --- a/boot/freeldr/freeldr/arch/i386/xbox/machxbox.c +++ b/boot/freeldr/freeldr/arch/i386/xbox/machxbox.c @@ -17,10 +17,13 @@ */ #include <freeldr.h> +#include <drivers/xbox/superio.h> #include <debug.h> DBG_DEFAULT_CHANNEL(HWDETECT); +#define MAX_XBOX_COM_PORTS 2 + extern PVOID FrameBuffer; extern ULONG FrameBufferSize; @@ -51,30 +54,19 @@ XboxGetSerialPort(ULONG Index, PULONG Irq) static const UCHAR Device[MAX_XBOX_COM_PORTS] = {LPC_DEVICE_SERIAL_PORT_1, LPC_DEVICE_SERIAL_PORT_2}; ULONG ComBase = 0; - // Enter Configuration - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_ENTER_CONFIG_KEY); + LpcEnterConfig(); // Select serial device - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_CONFIG_DEVICE_NUMBER); - WRITE_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1), Device[Index]); + LpcWriteRegister(LPC_CONFIG_DEVICE_NUMBER, Device[Index]); // Check if selected device is active - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_CONFIG_DEVICE_ACTIVATE); - if (READ_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1)) == 1) + if (LpcReadRegister(LPC_CONFIG_DEVICE_ACTIVATE) == 1) { - // Read LSB - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_CONFIG_DEVICE_BASE_ADDRESS_LOW); - ComBase = READ_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1)); - // Read MSB - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_CONFIG_DEVICE_BASE_ADDRESS_HIGH); - ComBase |= (READ_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1)) << 8); - // Read IRQ - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_CONFIG_DEVICE_INTERRUPT); - *Irq = READ_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1)); + ComBase = LpcGetIoBase(); + *Irq = LpcGetIrqPrimary(); } - // Exit Configuration - WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_EXIT_CONFIG_KEY); + LpcExitConfig(); return ComBase; } diff --git a/boot/freeldr/freeldr/include/arch/i386/machxbox.h b/boot/freeldr/freeldr/include/arch/i386/machxbox.h index d4342de4a0f..0ba3033ad06 100644 --- a/boot/freeldr/freeldr/include/arch/i386/machxbox.h +++ b/boot/freeldr/freeldr/include/arch/i386/machxbox.h @@ -22,21 +22,6 @@ #include "mm.h" #endif -#define MAX_XBOX_COM_PORTS 2 - -#define LPC_IO_BASE 0x2E -#define LPC_ENTER_CONFIG_KEY 0x55 -#define LPC_EXIT_CONFIG_KEY 0xAA - -#define LPC_DEVICE_SERIAL_PORT_1 0x4 -#define LPC_DEVICE_SERIAL_PORT_2 0x5 - -#define LPC_CONFIG_DEVICE_NUMBER 0x07 -#define LPC_CONFIG_DEVICE_ACTIVATE 0x30 -#define LPC_CONFIG_DEVICE_BASE_ADDRESS_HIGH 0x60 -#define LPC_CONFIG_DEVICE_BASE_ADDRESS_LOW 0x61 -#define LPC_CONFIG_DEVICE_INTERRUPT 0x70 - #define NV2A_CONTROL_OFFSET 0xFD000000 #define NV2A_FB_OFFSET (0x100000 + NV2A_CONTROL_OFFSET) #define NV2A_FB_CFG0 (0x200 + NV2A_FB_OFFSET) diff --git a/sdk/include/reactos/drivers/xbox/superio.h b/sdk/include/reactos/drivers/xbox/superio.h new file mode 100644 index 00000000000..ccb430c0fe5 --- /dev/null +++ b/sdk/include/reactos/drivers/xbox/superio.h @@ -0,0 +1,147 @@ +/* + * PROJECT: Original Xbox onboard hardware + * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later) + * PURPOSE: SMSC LPC47M157 (Super I/O) header file + * COPYRIGHT: Copyright 2020 Stanislav Motylkov ([email protected]) + */ + +#ifndef _SUPERIO_H_ +#define _SUPERIO_H_ + +#pragma once + +/* + * Registers and definitions + */ +#define LPC_IO_BASE 0x2E + +#define LPC_ENTER_CONFIG_KEY 0x55 +#define LPC_EXIT_CONFIG_KEY 0xAA + +#define LPC_DEVICE_FDD 0x0 +#define LPC_DEVICE_PARALLEL_PORT 0x3 +#define LPC_DEVICE_SERIAL_PORT_1 0x4 +#define LPC_DEVICE_SERIAL_PORT_2 0x5 +#define LPC_DEVICE_KEYBOARD 0x7 +#define LPC_DEVICE_GAME_PORT 0x9 +#define LPC_DEVICE_PME 0xA +#define LPC_DEVICE_MPU_401 0xB + +#define LPC_CONFIG_DEVICE_NUMBER 0x07 +#define LPC_CONFIG_DEVICE_ACTIVATE 0x30 +#define LPC_CONFIG_DEVICE_BASE_ADDRESS_HIGH 0x60 +#define LPC_CONFIG_DEVICE_BASE_ADDRESS_LOW 0x61 +#define LPC_CONFIG_DEVICE_INTERRUPT_PRIMARY 0x70 +#define LPC_CONFIG_DEVICE_INTERRUPT_SECONDARY 0x72 +#define LPC_CONFIG_DEVICE_DMA_CHANNEL 0x74 + +/* + * Functions + */ +FORCEINLINE +VOID +LpcEnterConfig(VOID) +{ + /* Enter Configuration */ + WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_ENTER_CONFIG_KEY); +} + +FORCEINLINE +VOID +LpcExitConfig(VOID) +{ + /* Exit Configuration */ + WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, LPC_EXIT_CONFIG_KEY); +} + +FORCEINLINE +UCHAR +LpcReadRegister(UCHAR Register) +{ + WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, Register); + return READ_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1)); +} + +FORCEINLINE +VOID +LpcWriteRegister(UCHAR Register, UCHAR Value) +{ + WRITE_PORT_UCHAR((PUCHAR)LPC_IO_BASE, Register); + WRITE_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1), Value); +} + +#ifndef __FREELDR_H +FORCEINLINE +ULONG +LpcDetectSuperIO(VOID) +{ + LpcEnterConfig(); + + LpcWriteRegister(LPC_CONFIG_DEVICE_NUMBER, LPC_DEVICE_SERIAL_PORT_1); + + if (READ_PORT_UCHAR((PUCHAR)(LPC_IO_BASE + 1)) != LPC_DEVICE_SERIAL_PORT_1) + return 0; + + if (LpcReadRegister(LPC_CONFIG_DEVICE_ACTIVATE) > 1) + return 0; + + LpcExitConfig(); + + return LPC_IO_BASE; +} +#endif + +FORCEINLINE +ULONG +LpcGetIoBase() +{ + ULONG Base = 0; + + // Read LSB + Base = LpcReadRegister(LPC_CONFIG_DEVICE_BASE_ADDRESS_LOW); + // Read MSB + Base |= (LpcReadRegister(LPC_CONFIG_DEVICE_BASE_ADDRESS_HIGH) << 8); + + return Base; +} + +#ifndef __FREELDR_H +FORCEINLINE +ULONG +LpcGetIoBaseMPU() +{ + ULONG Base = 0; + + // Read LSB + Base = LpcReadRegister(LPC_CONFIG_DEVICE_BASE_ADDRESS_HIGH); + // Read MSB + Base |= (LpcReadRegister(LPC_CONFIG_DEVICE_BASE_ADDRESS_LOW) << 8); + + return Base; +} +#endif + +FORCEINLINE +ULONG +LpcGetIrqPrimary() +{ + return LpcReadRegister(LPC_CONFIG_DEVICE_INTERRUPT_PRIMARY); +} + +#ifndef __FREELDR_H +FORCEINLINE +ULONG +LpcGetIrqSecondary() +{ + return LpcReadRegister(LPC_CONFIG_DEVICE_INTERRUPT_SECONDARY); +} + +FORCEINLINE +ULONG +LpcGetDmaChannel() +{ + return LpcReadRegister(LPC_CONFIG_DEVICE_DMA_CHANNEL); +} +#endif + +#endif /* _SUPERIO_H_ */
