On 31 October 2017 at 22:10, William Mahoney <wmaho...@unomaha.edu> wrote: > But of course the code writes to the interrupt controller > mask registers to enable and disable things. How does this > get “wired in” to qemu? I will need to tell it “yes you can > generate interrupt 27 now”? > > Just aim me at a good example if you know of one.
Interrupt controllers are all in hw/intc/. They're just devices with some input lines (incoming interrupts), some output lines (signalled to the CPU), and some registers (controlling the logic of when they raise/lower their output lines). (For some guest CPUs they don't actually model the line between interrupt controller and CPU specifically, but have a function call that does it.) There must already be an interrupt controller for your guest CPU type, so look at what it does. thanks -- PMM
