Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
configs/targets/hppa-linux-user.mak | 1 +
target/hppa/cpu-param.h | 23 +++++++----------------
target/hppa/cpu.h | 9 ---------
target/hppa/cpu.c | 4 ----
target/hppa/translate.c | 2 --
5 files changed, 8 insertions(+), 31 deletions(-)
diff --git a/configs/targets/hppa-linux-user.mak
b/configs/targets/hppa-linux-user.mak
index 361ea39d71..8e0a80492f 100644
--- a/configs/targets/hppa-linux-user.mak
+++ b/configs/targets/hppa-linux-user.mak
@@ -1,4 +1,5 @@
TARGET_ARCH=hppa
+TARGET_ABI32=y
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index c2791ae5f2..2fb8e7924b 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -8,26 +8,17 @@
#ifndef HPPA_CPU_PARAM_H
#define HPPA_CPU_PARAM_H
-#ifdef TARGET_HPPA64
-# define TARGET_LONG_BITS 64
-# define TARGET_REGISTER_BITS 64
-# define TARGET_VIRT_ADDR_SPACE_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 64
-#elif defined(CONFIG_USER_ONLY)
-# define TARGET_LONG_BITS 32
-# define TARGET_REGISTER_BITS 32
+#define TARGET_LONG_BITS 64
+#define TARGET_REGISTER_BITS 64
+
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32)
+# define TARGET_PHYS_ADDR_SPACE_BITS 32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
-# define TARGET_PHYS_ADDR_SPACE_BITS 32
#else
-/*
- * In order to form the GVA from space:offset,
- * we need a 64-bit virtual address space.
- */
-# define TARGET_LONG_BITS 64
-# define TARGET_REGISTER_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 64
# define TARGET_VIRT_ADDR_SPACE_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
+
#define TARGET_PAGE_BITS 12
#endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 1a12b2a186..251f85444a 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -107,11 +107,7 @@
#define PSW_T 0x01000000
#define PSW_S 0x02000000
#define PSW_E 0x04000000
-#ifdef TARGET_HPPA64
#define PSW_W 0x08000000 /* PA2.0 only */
-#else
-#define PSW_W 0
-#endif
#define PSW_Z 0x40000000 /* PA1.x only */
#define PSW_Y 0x80000000 /* PA1.x only */
@@ -124,13 +120,8 @@
#define PSW_SM_P PSW_P
#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
-#ifdef TARGET_HPPA64
#define PSW_SM_E 0x100
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
-#else
-#define PSW_SM_E 0
-#define PSW_SM_W 0
-#endif
#define CR_RC 0
#define CR_PID1 8
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 6bf415139f..bbb6080e2d 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -253,7 +253,6 @@ static const TypeInfo hppa_cpu_type_info = {
.class_init = hppa_cpu_class_init,
};
-#ifdef TARGET_HPPA64
static void hppa64_cpu_initfn(Object *obj)
{
HPPACPU *cpu = HPPA_CPU(obj);
@@ -265,14 +264,11 @@ static const TypeInfo hppa64_cpu_type_info = {
.parent = TYPE_HPPA_CPU,
.instance_init = hppa64_cpu_initfn,
};
-#endif
static void hppa_cpu_register_types(void)
{
type_register_static(&hppa_cpu_type_info);
-#ifdef TARGET_HPPA64
type_register_static(&hppa64_cpu_type_info);
-#endif
}
type_init(hppa_cpu_register_types)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8bea28f0fd..94969cf2f0 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2156,7 +2156,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
switch (ctl) {
case CR_SAR:
-#ifdef TARGET_HPPA64
if (a->e == 0) {
/* MFSAR without ,W masks low 5 bits. */
tmp = dest_gpr(ctx, rt);
@@ -2164,7 +2163,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
save_gpr(ctx, rt, tmp);
goto done;
}
-#endif
save_gpr(ctx, rt, cpu_sar);
goto done;
case CR_IT: /* Interval Timer */
--
2.34.1
