On Thu, 28 Sept 2023 at 10:44, Michal Orzel <michal.or...@amd.com> wrote:
>
> On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top
> of Xen, a trap from EL2 was observed which is something not reproducible
> on HW (also, Xen does not trap accesses to physical counter).
>
> This is because gt_counter_access() checks for an incorrect bit (1
> instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to
> physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2:
> When HCR_EL2.E2H is 0:
> - EL1PCTEN, bit [0]: refers to physical counter
> - EL1PCEN, bit [1]: refers to physical timer registers
>
> Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case
> and fall through to EL1 case, given that after fixing checking for the
> correct bit, the handling is the same.
>
> Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE")
> Signed-off-by: Michal Orzel <michal.or...@amd.com>
Applied to target-arm.next, thanks (sorry for the delay; I've
been on holiday ;-)).
-- PMM
