Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/insns.decode | 2 ++
target/sparc/translate.c | 41 +++++++++++++++++++++++++++++++++++----
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index a95f682fa7..87108da5da 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -172,3 +172,5 @@ ORN 10 ..... 000110 ..... . .............
@r_r_ri
ORNcc 10 ..... 010110 ..... . ............. @r_r_ri
XORN 10 ..... 000111 ..... . ............. @r_r_ri
XORNcc 10 ..... 010111 ..... . ............. @r_r_ri
+ADDC 10 ..... 001000 ..... . ............. @r_r_ri
+ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index a21c5ec329..37917ad397 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4159,6 +4159,43 @@ TRANS(ANDNcc, ALL, do_cc_arith, a, CC_OP_LOGIC,
tcg_gen_andc_tl, NULL)
TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL)
TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL)
+static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm)
+{
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!imm && rs2_or_imm & ~0x1f) {
+ return NULL;
+ }
+ if (imm || rs2_or_imm == 0) {
+ return tcg_constant_tl(rs2_or_imm);
+ } else {
+ return cpu_regs[rs2_or_imm];
+ }
+}
+
+static bool trans_ADDC(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_op_addx_int(dc, gen_dest_gpr(dc, a->rd),
+ gen_load_gpr(dc, a->rs1), src2, false);
+ return advance_pc(dc);
+}
+
+static bool trans_ADDCcc(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_op_addx_int(dc, gen_dest_gpr(dc, a->rd),
+ gen_load_gpr(dc, a->rs1), src2, true);
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4583,10 +4620,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
- case 0x8: /* addx, V9 addc */
- gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
- (xop & 0x10));
- break;
#ifdef TARGET_SPARC64
case 0x9: /* V9 mulx */
tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
--
2.34.1
