On Mon, Oct 02, 2023 at 01:39:16PM +0200, Marcin Juszkiewicz wrote: > W dniu 8.09.2023 o 15:29, Marcin Juszkiewicz pisze: > > W dniu 31.08.2023 o 12:05, Marcin Juszkiewicz pisze: > > > W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze: > > > > current code sets PCI_SEC_LATENCY_TIMER to WO, but for > > > > pcie to pcie bridges it must be RO 0 according to > > > > pci express spec which says: > > > > This register does not apply to PCI Express. It must be read-only > > > > and hardwired to 00h. For PCI Express to PCI/PCI-X Bridges, > > > > refer to the > > > > [PCIe-to-PCI-PCI-X-Bridge] for requirements for this register. > > > > > > > > also, fix typo in comment where it's make writeable - this typo > > > > is likely what prevented us noticing we violate this requirement > > > > in the 1st place. > > > > > > > > Reported-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org> > > > > Signed-off-by: Michael S. Tsirkin <m...@redhat.com> > > > > --- > > > > > > > Marcin, could you pls test this patch with virt-8.1 and latest? > > > > Thanks a lot! > > > > > > Tested-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org> > > > > > > sbsa-ref: PASS > > > virt: PASS > > > virt-8.1: FAIL (as expected) > > > virt-8.0: FAIL (as expected) > > > > Can we get this patch refreshed and merged? > > ping? >
yes, working on a pull request including this.
