Ping.
r~
On 9/16/23 15:01, Richard Henderson wrote:
For tcg generated code, use new registers with load so that we never
overlap the input address, so that we can simplify address build for
64-bit user-only.
For tcg out-of-line code, implement the host/ headers to for atomic 128-bit
load and store, reducing the cases for which we must raise EXCP_ATOMIC.
r~
Based-on: 20230916171223.521545-1-richard.hender...@linaro.org
("[PULL v2 00/39] tcg patch queue")
Richard Henderson (7):
tcg: Add C_N2_I1
tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
util: Add cpuinfo for loongarch64
tcg/loongarch64: Use cpuinfo.h
host/include/loongarch64: Add atomic16 load and store
accel/tcg: Remove redundant case in store_atom_16
accel/tcg: Fix condition for store_atom_insert_al16
.../include/loongarch64/host/atomic128-ldst.h | 52 +++++++++++++++++++
host/include/loongarch64/host/cpuinfo.h | 21 ++++++++
.../loongarch64/host/load-extract-al16-al8.h | 39 ++++++++++++++
.../loongarch64/host/store-insert-al16.h | 12 +++++
tcg/loongarch64/tcg-target-con-set.h | 2 +-
tcg/loongarch64/tcg-target.h | 8 +--
accel/tcg/cputlb.c | 2 +-
tcg/tcg.c | 5 ++
util/cpuinfo-loongarch.c | 35 +++++++++++++
accel/tcg/ldst_atomicity.c.inc | 14 ++---
tcg/loongarch64/tcg-target.c.inc | 25 +++++----
util/meson.build | 2 +
12 files changed, 189 insertions(+), 28 deletions(-)
create mode 100644 host/include/loongarch64/host/atomic128-ldst.h
create mode 100644 host/include/loongarch64/host/cpuinfo.h
create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h
create mode 100644 host/include/loongarch64/host/store-insert-al16.h
create mode 100644 util/cpuinfo-loongarch.c
