On a real UltraSparc II CPU, the fmul8x16 instruction reads its first input from any of the single-precision floating point registers.
But the emulator is reading the input as if the first operand encodes a double-precision register, which in most cases will not contain the right data and therefore the output of the emulated instruction is just garbage. Signed-off-by: Nick Bowler <nbow...@draconx.ca> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1901 --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 6 +++++- target/sparc/vis_helper.c | 9 +++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b8f1e78c75..ace731a22c 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -126,7 +126,7 @@ DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3bf0ab8135..bb65b8daf8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4750,7 +4750,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x031: /* VIS I fmul8x16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(dc, rd); + gen_helper_fmul8x16(cpu_dst_64, cpu_src1_32, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x033: /* VIS I fmul8x16au */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 3afdc6975c..d158b39b85 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -94,16 +94,17 @@ uint64_t helper_fpmerge(uint64_t src1, uint64_t src2) return d.ll; } -uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2) +uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2) { - VIS64 s, d; + VIS32 s; + VIS64 d; uint32_t tmp; - s.ll = src1; + s.l = src1; d.ll = src2; #define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ + tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B32(r); \ if ((tmp & 0xff) > 0x7f) { \ tmp += 0x100; \ } \ -- 2.41.0
