On Fri, 2023-09-01 at 17:57 +0200, Nina Schoetterl-Glausch wrote: > From: Pierre Morel <pmo...@linux.ibm.com> > > On interception of STSI(15.1.x) the System Information Block > (SYSIB) is built from the list of pre-ordered topology entries. > > Signed-off-by: Pierre Morel <pmo...@linux.ibm.com> > Co-developed-by: Nina Schoetterl-Glausch <n...@linux.ibm.com> > Signed-off-by: Nina Schoetterl-Glausch <n...@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <n...@linux.ibm.com> > --- > MAINTAINERS | 1 + > qapi/machine-target.json | 14 ++ > include/hw/s390x/cpu-topology.h | 25 +++ > include/hw/s390x/sclp.h | 1 + > target/s390x/cpu.h | 76 ++++++++ > hw/s390x/cpu-topology.c | 2 + > target/s390x/kvm/kvm.c | 5 +- > target/s390x/kvm/stsi-topology.c | 296 +++++++++++++++++++++++++++++++ > target/s390x/kvm/meson.build | 3 +- > 9 files changed, 421 insertions(+), 2 deletions(-) > create mode 100644 target/s390x/kvm/stsi-topology.c [...] > +/* > + * CPU Topology List provided by STSI with fc=15 provides a list > + * of two different Topology List Entries (TLE) types to specify > + * the topology hierarchy. > + * > + * - Container Topology List Entry > + * Defines a container to contain other Topology List Entries > + * of any type, nested containers or CPU. > + * - CPU Topology List Entry > + * Specifies the CPUs position, type, entitlement and polarization > + * of the CPUs contained in the last Container TLE. > + * > + * There can be theoretically up to five levels of containers, QEMU > + * uses only three levels, the drawer's, book's and socket's level. > + * > + * A container with a nesting level (NL) greater than 1 can only > + * contain another container of nesting level NL-1. > + * > + * A container of nesting level 1 (socket), contains as many CPU TLE > + * as needed to describe the position and qualities of all CPUs inside > + * the container. > + * The qualities of a CPU are polarization, entitlement and type. > + * > + * The CPU TLE defines the position of the CPUs of identical qualities > + * using a 64bits mask which first bit has its offset defined by > + * the CPU address orgin field of the CPU TLE like in: s/orgin/origin/ > + * CPU address = origin * 64 + bit position within the mask > + * > + */ [...] > diff --git a/target/s390x/kvm/stsi-topology.c > b/target/s390x/kvm/stsi-topology.c > new file mode 100644 > index 0000000000..cb78040ea5 > --- /dev/null > +++ b/target/s390x/kvm/stsi-topology.c [...] > +/** > + * setup_stsi: > + * sysib: pointer to a SysIB to be filled with SysIB_151x data > + * level: Nested level specified by the guest No @ in front of the arguments here. > + * > + * Setup the SYSIB for STSI 15.1, the header as well as the description > + * of the topology. > + */ > +static int setup_stsi(S390TopologyList *topology_list, SysIB_151x *sysib, > + int level) [...]
