On Tue, 2023-08-29 at 17:50 -0400, leon@is.currently.online wrote:
> From: Leon Schuermann <le...@opentitan.org>
>
> When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the
> PMP
> configuration lock bits must not apply. While this behavior is
> implemented for the pmpcfgX CSRs, this bit is not respected for
> changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
> writes work even on locked regions when the global rule-lock bypass
> is
> enabled.
>
> Signed-off-by: Leon Schuermann <le...@opentitan.org>
> ---
> target/riscv/pmp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 9d8db493e6..5e60c26031 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
> */
> static inline int pmp_is_locked(CPURISCVState *env, uint32_t
> pmp_index)
> {
> + /* mseccfg.RLB is set */
> + if (MSECCFG_RLB_ISSET(env)) {
> + return 0;
> + }
>
> if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
> return 1;
>
> base-commit: a8fc5165aab02f328ccd148aafec1e59fd1426eb
Reviewed-by: Mayuresh Chitale <mchit...@ventanamicro.com>
