On Fri, 11 Aug 2023 at 22:42, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> The cortex-a710 is a first generation ARMv9.0-A processor.
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index b12e10d3ab..81c27c70e8 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -758,6 +758,239 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> aarch64_add_sve_properties(obj);
> }
>
> +static bool trap_tidcp(CPUARMState *env)
> +{
> + return arm_current_el(env) < 2 && (arm_hcr_el2_eff(env) & HCR_TIDCP);
> +}
> +
> +static CPAccessResult access_tidcp(CPUARMState *env, const ARMCPRegInfo *r,
> + bool read)
> +{
> + return trap_tidcp(env) ? CP_ACCESS_TRAP_EL2 : CP_ACCESS_OK;
> +}
> +
> +static CPAccessResult access_tidcp_actlr_w(CPUARMState *env,
> + const ARMCPRegInfo *r, bool read)
> +{
> + if (trap_tidcp(env)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + return access_actlr_w(env, r, read);
> +}
HCR_EL2.TIDCP traps accesses to a whole IMPDEF range, not
just to the registers that the implementation happens to
define. We should implement this in translate.c, translate-a64.c
and op_helper.c in a similar way to what we do for the aa64_ids
feature, so that we correctly prioritize the trap over the
UNDEF for registers in the space that don't exist, and so
that we don't need to explicitly add the TICDP check to
every IMPDEF register.
Since we already don't implement this correctly for the
other CPUs, we don't need to gate Cortex-A710 on doing
it right.
thanks
-- PMM
