On Wed, Aug 23, 2023 at 3:54 PM Michael Tokarev <m...@tls.msk.ru> wrote:
>
> Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/virt.c | 4 ++--
> include/hw/riscv/riscv_hart.h | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu_bits.h | 4 ++--
> target/riscv/csr.c | 4 ++--
> target/riscv/debug.c | 10 +++++-----
> target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvzfh.c.inc | 4 ++--
> target/riscv/monitor.c | 2 +-
> 11 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e81bbd12df..b775aa8946 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -660,5 +660,5 @@ static void
> microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
>
> /*
> - * Map 513 MiB high memory, the mimimum required high memory size,
> because
> + * Map 513 MiB high memory, the minimum required high memory size,
> because
> * HSS will do memory test against the high memory address range
> regardless
> * of physical memory installed.
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 99c4e6314b..a5ac3ab777 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -67,5 +67,5 @@
> #if VIRT_IMSIC_GROUP_MAX_SIZE < \
> IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
> -#error "Can't accomodate single IMSIC group in address space"
> +#error "Can't accommodate single IMSIC group in address space"
> #endif
>
> @@ -73,5 +73,5 @@
> VIRT_IMSIC_GROUP_MAX_SIZE)
> #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
> -#error "Can't accomodate all IMSIC groups in address space"
> +#error "Can't accommodate all IMSIC groups in address space"
> #endif
>
> diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
> index bbc21cdc9a..912b4a2682 100644
> --- a/include/hw/riscv/riscv_hart.h
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -4,5 +4,5 @@
> * Copyright (c) 2017 SiFive, Inc.
> *
> - * Holds the state of a heterogenous array of RISC-V harts
> + * Holds the state of a heterogeneous array of RISC-V harts
> *
> * This program is free software; you can redistribute it and/or modify it
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6ea22e0eea..6316cbcc23 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -350,5 +350,5 @@ struct CPUArchState {
> target_ulong upmbase;
>
> - /* CSRs for execution enviornment configuration */
> + /* CSRs for execution environment configuration */
> uint64_t menvcfg;
> uint64_t mstateen[SMSTATEEN_MAX_COUNT];
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 59f0ffd9e1..31a8d80990 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -657,5 +657,5 @@ typedef enum {
> #define PGSHIFT 12
>
> -/* Default Reset Vector adress */
> +/* Default Reset Vector address */
> #define DEFAULT_RSTVEC 0x1000
>
> @@ -741,5 +741,5 @@ typedef enum RISCVException {
> #define PM_INSN 0x00000004ULL
>
> -/* Execution enviornment configuration bits */
> +/* Execution environment configuration bits */
> #define MENVCFG_FIOM BIT(0)
> #define MENVCFG_CBIE (3UL << 4)
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ea7585329e..26bc1f0ff1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3217,5 +3217,5 @@ static int write_hvipriox(CPURISCVState *env, int
> first_index,
> }
>
> - /* Fill-up priority arrary */
> + /* Fill-up priority array */
> for (i = 0; i < num_irqs; i++) {
> if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> @@ -3886,5 +3886,5 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
> !env->virt_enabled) {
> /*
> - * We are in HS mode. Add 1 to the effective privledge level to
> + * We are in HS mode. Add 1 to the effective privilege level to
> * allow us to access the Hypervisor CSRs.
> */
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 75ee1c4971..211f5921b6 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -575,5 +575,5 @@ static void riscv_itrigger_update_count(CPURISCVState
> *env)
> /*
> * Record last icount, so that we can evaluate the executed instructions
> - * since last priviledge mode change or timer expire.
> + * since last privilege mode change or timer expire.
> */
> int64_t last_icount = env->last_icount, current_icount;
> @@ -589,5 +589,5 @@ static void riscv_itrigger_update_count(CPURISCVState
> *env)
> }
> /*
> - * Only when priviledge is changed or itrigger timer expires,
> + * Only when privilege is changed or itrigger timer expires,
> * the count field in itrigger tdata1 register is updated.
> * And the count field in itrigger only contains remaining value.
> @@ -595,6 +595,6 @@ static void riscv_itrigger_update_count(CPURISCVState
> *env)
> if (check_itrigger_priv(env, i)) {
> /*
> - * If itrigger enabled in this priviledge mode, the number of
> - * executed instructions since last priviledge change
> + * If itrigger enabled in this privilege mode, the number of
> + * executed instructions since last privilege change
> * should be reduced from current itrigger count.
> */
> @@ -606,5 +606,5 @@ static void riscv_itrigger_update_count(CPURISCVState
> *env)
> } else {
> /*
> - * If itrigger is not enabled in this priviledge mode,
> + * If itrigger is not enabled in this privilege mode,
> * the number of executed instructions will be discard and
> * the count field in itrigger will not change.
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
> b/target/riscv/insn_trans/trans_rvf.c.inc
> index a0da7391c7..e7ab84cd9a 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -301,5 +301,5 @@ static bool trans_fsgnjn_s(DisasContext *ctx,
> arg_fsgnjn_s *a)
> tcg_gen_or_i64(dest, dest, rs2);
> }
> - /* signed-extended intead of nanboxing for result if enable zfinx */
> + /* signed-extended instead of nanboxing for result if enable zfinx */
> if (ctx->cfg_ptr->ext_zfinx) {
> tcg_gen_ext32s_i64(dest, dest);
> @@ -346,5 +346,5 @@ static bool trans_fsgnjx_s(DisasContext *ctx,
> arg_fsgnjx_s *a)
> tcg_gen_xor_i64(dest, rs1, dest);
> }
> - /* signed-extended intead of nanboxing for result if enable zfinx */
> + /* signed-extended instead of nanboxing for result if enable zfinx */
> if (ctx->cfg_ptr->ext_zfinx) {
> tcg_gen_ext32s_i64(dest, dest);
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index c2f7527f53..6ab63f4442 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2241,5 +2241,5 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)
> * If SEW < FLEN, check whether input fp register is a valid
> * NaN-boxed value, in which case the least-significant SEW bits
> - * of the f regsiter are used, else the canonical NaN value is used.
> + * of the f register are used, else the canonical NaN value is used.
> */
> static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
> @@ -3283,5 +3283,5 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
> }
>
> -/* offset of the idx element with base regsiter r */
> +/* offset of the idx element with base register r */
> static uint32_t endian_ofs(DisasContext *s, int r, int idx)
> {
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
> b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 8b1e2519bb..4b01812fd8 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -306,5 +306,5 @@ static bool trans_fsgnjn_h(DisasContext *ctx,
> arg_fsgnjn_h *a)
> tcg_gen_or_i64(dest, dest, rs2);
> }
> - /* signed-extended intead of nanboxing for result if enable zfinx */
> + /* signed-extended instead of nanboxing for result if enable zfinx */
> if (ctx->cfg_ptr->ext_zfinx) {
> tcg_gen_ext16s_i64(dest, dest);
> @@ -350,5 +350,5 @@ static bool trans_fsgnjx_h(DisasContext *ctx,
> arg_fsgnjx_h *a)
> tcg_gen_xor_i64(dest, rs1, dest);
> }
> - /* signed-extended intead of nanboxing for result if enable zfinx */
> + /* signed-extended instead of nanboxing for result if enable zfinx */
> if (ctx->cfg_ptr->ext_zfinx) {
> tcg_gen_ext16s_i64(dest, dest);
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index f36ddfa967..f5b1ffe6c3 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -56,5 +56,5 @@ static void print_pte(Monitor *mon, int va_bits,
> target_ulong vaddr,
> hwaddr paddr, target_ulong size, int attr)
> {
> - /* santity check on vaddr */
> + /* sanity check on vaddr */
> if (vaddr >= (1UL << va_bits)) {
> return;
> --
> 2.39.2
>
>
