Hi. I need to model some custom HW that synchronizes CPUs when they read MMIO register N: MMIO read does not return until another CPU writes to MMIO register M. I modeled this behavior with a) on MMIO read of N, save CPU into a list of waiting CPUs and put it asleep with cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT) and b) on MMIO write to M, wake all waiting CPUs with cpu->halted = 0; qemu_cpu_kick(cpu). It seems to work fine. However, this HW has a twist: MMIO read of N returns a value that was written by MMIO write to M. Can anyone please advise how this could be done?
Thanks! Igor
