[PATCH 2/2] riscv: zicond: make default

[Vineet Gupta]

Again this helps with better testing and something qemu has been doing
with newer features anyways.

Signed-off-by: Vineet Gupta <vine...@rivosinc.com>
---
 target/riscv/cpu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 022bd9d01223..e6e28414b223 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -438,6 +438,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.ext_xtheadbs = true;
     cpu->cfg.ext_xtheadcmo = true;
     cpu->cfg.ext_xtheadcondmov = true;
+    cpu->cfg.ext_zicond = false;
     cpu->cfg.ext_xtheadfmemidx = true;
     cpu->cfg.ext_xtheadmac = true;
     cpu->cfg.ext_xtheadmemidx = true;
@@ -483,6 +484,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
     cpu->cfg.ext_zbc = true;
     cpu->cfg.ext_zbs = true;
     cpu->cfg.ext_XVentanaCondOps = true;
+    cpu->cfg.ext_zicond = false;
 
     cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
     cpu->cfg.marchid = VEYRON_V1_MARCHID;
@@ -1816,7 +1818,7 @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
     DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
-    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
+    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, true),
 
     /* Vendor-specific custom extensions */
     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
-- 
2.34.1