One line patch that fixes the issue reported in: https://gitlab.com/qemu-project/qemu/-/issues/1793
>From 7122a450d745325ce250785e58c543481054bec6 Mon Sep 17 00:00:00 2001 From: "Nathan E. Egge" <[email protected]> Date: Mon, 31 Jul 2023 03:45:13 -0400 Subject: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V
Set V bit for hwcap if misa is set. Signed-off-by: Nathan E. Egge <[email protected]> --- linux-user/elfload.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 861ec07abc..a299ba7300 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) #define MISA_BIT(EXT) (1 << (EXT - 'A')) RISCVCPU *cpu = RISCV_CPU(thread_cpu); uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') + | MISA_BIT('V'); return cpu->env.misa_ext & mask; #undef MISA_BIT -- 2.35.1
