On Thu, Jun 8, 2023 at 3:32 PM Xiao Wang <xiao.w.w...@intel.com> wrote: > > There's no code using MTYPE, which was a concept used in older vector > implementation. > > Signed-off-by: Xiao Wang <xiao.w.w...@intel.com>
Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/vector_helper.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index f261e726c2..1e06e7447c 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -378,7 +378,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState > *env, uint32_t desc, > > /* > * masked unit-stride load and store operation will be a special case of > - * stride, stride = NF * sizeof (MTYPE) > + * stride, stride = NF * sizeof (ETYPE) > */ > > #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ > @@ -650,10 +650,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) > #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) > #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) > > -/* Unsigned min/max */ > -#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) > -#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) > - > /* > * load and store whole register instructions > */ > -- > 2.25.1 > >
