On 2023/6/1 1:47, Richard Henderson wrote:
On 5/30/23 23:54, LIU Zhiwei wrote:
We missed these functions when upstreaming the bfloat16 support.
Signed-off-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
They look ok, so far as it goes. What will they be used for?
T-Head Xuantie CPUs custom extension need these interfaces. It uses a
custom CSR(still not upstream) to switch between the fp16 and bfloat16.
All fp16 instructions(Zfh) can process the bfloat16 types. In its custom
matrix extension[1] or vector extension, this feature is also supported.
As a side note, the RISC-V port support for custom extension at least
should have these aspects:
* ISA decoding (Ready, Philipp Tomsich)
* CSR (WIP, Andes?)
* Disassemble(Under review, Christopher)
* Errata(Not start)
* Split TB flags like ARM for custom(In the wild for the Xuantie CPUs)
1.
https://github.com/T-head-Semi/riscv-matrix-extension-spec/releases/tag/v0.1.0
r~
