This patch series adds stage-2 translation support for SMMUv3. It is controlled by a new system property “arm-smmuv3.stage”. - When set to “1”: Stage-1 only would be advertised and supported (default behaviour) - When set to “2”: Stage-2 only would be advertised and supported.
Features implemented in stage-2 are mostly synonymous with stage-1 - VMID16. - Only AArch64 translation tables are supported. - Only little endian translation table supported. - Stall is not supported. - HTTU is not supported, SW is expected to maintain the Access flag. To make it easy to support nesting, a new structure(SMMUS2Cfg) is embedded within SMMUTransCfg, to hold stage-2 configuration. TLBs were updated to support VMID, where when stage-2 is used ASID is set to -1 and ignored and when stage-1 is used VMID is set to -1 and ignored. As only one stage is supported at a time at the moment, TLB will represent IPA=>PA translation with proper attributes(granularity and t0sz) parsed from STEs for stage-2, and will represent VA=>PA translation with proper attributes parsed from the CDs for stage-1. New commands where added that are used with stage-2 - CMD_TLBI_S12_VMALL: Invalidate all translations for a VMID. - CMD_TLBI_S2_IPA: Invalidate stage-2 by VMID and IPA Some commands are illegal to be used from stage-2 were modified to return CERROR_ILL. This patch series can be used to run Linux pKVM SMMUv3 patches (currently on the list) which controls stage-2 (from EL2) while providing a paravirtualized interface the host(EL1) https://lore.kernel.org/kvmarm/20230201125328.2186498-1-jean-phili...@linaro.org/ Looking forward, nesting is the next feature to go for, here are some thoughts about this: - TLB would require big changes for this, we can go either for a combined implementation or per stage one. This would affect returns from PTW and invalidation commands. - Stage-1 data structures should be translated by stage-2 if enabled (as context descriptors and ttb0/ttb1) - Translated addresses from stage-1 should be translated by stage-2 if enabled. - Some existing commands(as CMD_TLBI_S2_IPA, CMD_TLBI_NH_ASID …) would be modified and some of those would be based on the design of the TLBs. - Currently, VMID is ignored when stage-1 is used as it can’t be used with stage-2. However when nesting is advertised VMID shouldn’t be ignored even if stage-2 is bypassed. Changes in v4: - Collected Reviewed-by tags - Add SMMU_CMD_TLBI_S12_VMALL in a block to fix compilation issue - Simplify record fault macro - Remove references to "all" stage Changes in v3: - Collected Reviewed-by tags - Separate stage-2 record faults from stage-1 - Fix input address check in stage-2 walk - Fix shift in STE_S2HD, STE_S2HA, STE_S2S, STE_S2R - Add more logs for illegal configs and commands. - Rename SMMU translation macros to VMSA as they are not part of SMMU spec - Rename stage-2 variables and functions (iova=>ipa, ap=>s2ap, ...) - Rename oas in SMMUS2Cfg to eff_ps - Improve comments (mention user manuals versions, field names) Changes in v2: -Collected Reviewed-by tags -Add oas to SMMUS2Cfg, and use it in PTW -Add stage member to to SMMUPTWEventInfo to differentiate stage-1 and stage-2 PTW faults -Move stage-2 knob to the last patch -Add all STE parsing in one patch -Pares and use S2PS and S2ENDI -Split S2AFF patch over PTW and STE patches. -Fix TLB aliasing issue -Renaming and refactoring and rewording commits. -Populate OAS based on PARANGE -Add checks for stage-1 only commands -Update trace events to hold translation stage, vmid when possible -Remove feature flags for supported stages as they were redundant with IDR0 Mostafa Saleh (10): hw/arm/smmuv3: Add missing fields for IDR0 hw/arm/smmuv3: Update translation config to hold stage-2 hw/arm/smmuv3: Refactor stage-1 PTW hw/arm/smmuv3: Add page table walk for stage-2 hw/arm/smmuv3: Parse STE config for stage-2 hw/arm/smmuv3: Make TLB lookup work for stage-2 hw/arm/smmuv3: Add VMID to TLB tagging hw/arm/smmuv3: Add CMDs related to stage-2 hw/arm/smmuv3: Add stage-2 support in iova notifier hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 hw/arm/smmu-common.c | 209 +++++++++++++++++--- hw/arm/smmu-internal.h | 37 ++++ hw/arm/smmuv3-internal.h | 12 +- hw/arm/smmuv3.c | 357 ++++++++++++++++++++++++++++++----- hw/arm/trace-events | 14 +- include/hw/arm/smmu-common.h | 45 ++++- include/hw/arm/smmuv3.h | 4 + 7 files changed, 587 insertions(+), 91 deletions(-) -- 2.40.1.606.ga4b1b128d6-goog
