On 5/6/23 07:52, Richard Purdie wrote:
The following commits changed the code such that the fallback to MFSS for
MFFSCRN,
MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal
instruction:
bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to
decodetree
394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to
decodetree
3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to
decodetree
The hardware will handle them as a MFFS instruction as the code did previously.
This means applications that were segfaulting under qemu when encountering these
instructions which is used in glibc libm functions for example.
The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing.
This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs
as the hardware decoder would, fixing the segfaulting libm code. It and also
ensures
the MFSS instruction is used for currently reserved bits to handle other
potential
ISA additions more correctly.
Signed-off-by: Richard Purdie<richard.pur...@linuxfoundation.org>
---
target/ppc/insn32.decode | 19 ++++++++++++-------
target/ppc/translate/fp-impl.c.inc | 30 ++++++++++++++++++++++++------
2 files changed, 36 insertions(+), 13 deletions(-)
v2 - switch to use decodetree pattern groups per feedback
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
