Create a CPU subclass, and register classes matching all CPU models except for "pxa270", which is an alias for "pxa270-a0".
Make arm_cpu_list() enumerate CPU subclasses. Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the CPUID in the class. NB: CPUIDs were first introduced by Paul Brook in r1765 (2006). Signed-off-by: Andreas Färber <afaer...@suse.de> Cc: Anthony Liguori <anth...@codemonkey.ws> Cc: Paul Brook <p...@codesourcery.com> Cc: Peter Maydell <peter.mayd...@linaro.org> --- Makefile.target | 1 + target-arm/cpu-core.h | 59 +++++++++++++++ target-arm/cpu.c | 190 +++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/cpu.h | 1 - target-arm/helper.c | 85 +++++++--------------- 5 files changed, 277 insertions(+), 59 deletions(-) create mode 100644 target-arm/cpu-core.h create mode 100644 target-arm/cpu.c diff --git a/Makefile.target b/Makefile.target index 68481a3..5c139be 100644 --- a/Makefile.target +++ b/Makefile.target @@ -80,6 +80,7 @@ endif libobj-$(TARGET_SPARC64) += vis_helper.o libobj-$(CONFIG_NEED_MMU) += mmu.o libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o +libobj-$(TARGET_ARM) += cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o libobj-y += cpu_init.o diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h new file mode 100644 index 0000000..3e8f046 --- /dev/null +++ b/target-arm/cpu-core.h @@ -0,0 +1,59 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * <http://www.gnu.org/licenses/old-licenses/gpl-2.0> + */ +#ifndef QEMU_ARM_CPU_CORE_H +#define QEMU_ARM_CPU_CORE_H + +#include "qemu/cpu.h" + +#define TYPE_ARM_CPU "arm-cpu" + +#define ARM_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) +#define ARM_CPU(obj) \ + OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) +#define ARM_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) + +/** + * ARMCPUClass: + * + * An ARM CPU model. + */ +typedef struct ARMCPUClass { + /*< private >*/ + CPUClass parent_class; + + struct { + uint32_t c0_cpuid; + } cp15; +} ARMCPUClass; + +/** + * ARMCPU: + * + * An ARM CPU core. + */ +typedef struct ARMCPU { + /*< private >*/ + CPU parent_obj; +} ARMCPU; + + +#endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c new file mode 100644 index 0000000..9255a19 --- /dev/null +++ b/target-arm/cpu.c @@ -0,0 +1,190 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * <http://www.gnu.org/licenses/old-licenses/gpl-2.0> + */ + +#include "cpu-core.h" +#include "qemu-common.h" + +static void arm_cpu_reset(CPU *c) +{ + cpu_common_reset(c); +} + +/* CPU models */ + +typedef struct ARMCPUInfo { + const char *name; + uint32_t id; +} ARMCPUInfo; + +static const ARMCPUInfo arm_cpus[] = { + { + .name = "arm926", + .id = 0x41069265, + }, + { + .name = "arm946", + .id = 0x41059461, + }, + { + .name = "arm1026", + .id = 0x4106a262, + }, + /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + */ + { + .name = "arm1136-r2", + .id = 0x4107b362, + }, + { + .name = "arm1136", + .id = 0x4117b363, + }, + { + .name = "arm1176", + .id = 0x410fb767, + }, + { + .name = "arm11mpcore", + .id = 0x410fb022, + }, + { + .name = "cortex-m3", + .id = 0x410fc231, + }, + { + .name = "cortex-a8", + .id = 0x410fc080, + }, + { + .name = "cortex-a9", + .id = 0x410fc090, + }, + { + .name = "cortex-a15", + .id = 0x412fc0f1, + }, + { + .name = "ti925t", + .id = 0x54029252, + }, + { + .name = "sa1100", + .id = 0x4401A11B, + }, + { + .name = "sa1110", + .id = 0x6901B119, + }, + { + .name = "pxa250", + .id = 0x69052100, + }, + { + .name = "pxa255", + .id = 0x69052d00, + }, + { + .name = "pxa260", + .id = 0x69052903, + }, + { + .name = "pxa261", + .id = 0x69052d05, + }, + { + .name = "pxa262", + .id = 0x69052d06, + }, + { + .name = "pxa270-a0", + .id = 0x69054110, + }, + { + .name = "pxa270-a1", + .id = 0x69054111, + }, + { + .name = "pxa270-b0", + .id = 0x69054112, + }, + { + .name = "pxa270-b1", + .id = 0x69054113, + }, + { + .name = "pxa270-c0", + .id = 0x69054114, + }, + { + .name = "pxa270-c5", + .id = 0x69054117, + }, + { + .name = "any", + .id = 0xffffffff, + }, +}; + +static void arm_cpu_class_init(ObjectClass *klass, void *data) +{ + ARMCPUClass *k = ARM_CPU_CLASS(klass); + CPUClass *cpu_class = CPU_CLASS(klass); + const ARMCPUInfo *info = data; + + cpu_class->reset = arm_cpu_reset; + + k->cp15.c0_cpuid = info->id; +} + +static void cpu_register(const ARMCPUInfo *info) +{ + TypeInfo type = { + .name = info->name, + .parent = TYPE_ARM_CPU, + .instance_size = sizeof(ARMCPU), + .class_size = sizeof(ARMCPUClass), + .class_init = arm_cpu_class_init, + .class_data = (void *)info, + }; + + type_register_static(&type); +} + +static TypeInfo arm_cpu_type_info = { + .name = TYPE_ARM_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(ARMCPU), + .abstract = true, + .class_size = sizeof(ARMCPUClass), +}; + +static void arm_cpu_types_init(void) +{ + int i; + + type_register_static(&arm_cpu_type_info); + for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { + cpu_register(&arm_cpus[i]); + } +} + +type_init(arm_cpu_types_init) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0d9b39c..5905ef2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -420,7 +420,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_PXA260 0x69052903 #define ARM_CPUID_PXA261 0x69052d05 #define ARM_CPUID_PXA262 0x69052d06 -#define ARM_CPUID_PXA270 0x69054110 #define ARM_CPUID_PXA270_A0 0x69054110 #define ARM_CPUID_PXA270_A1 0x69054111 #define ARM_CPUID_PXA270_B0 0x69054112 diff --git a/target-arm/helper.c b/target-arm/helper.c index ea4f35f..d8425db 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -11,6 +11,7 @@ #include "hw/loader.h" #endif #include "sysemu.h" +#include "cpu-core.h" static uint32_t cortexa15_cp15_c0_c1[8] = { 0x00001131, 0x00011011, 0x02010555, 0x00000000, @@ -51,8 +52,6 @@ static uint32_t arm1176_cp15_c0_c1[8] = static uint32_t arm1176_cp15_c0_c2[8] = { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; -static uint32_t cpu_arm_find_by_name(const char *name); - static inline void set_feature(CPUARMState *env, int feature) { env->features |= 1u << feature; @@ -400,13 +399,21 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) CPUARMState *cpu_arm_init(const char *cpu_model) { + ObjectClass *klass; + ARMCPUClass *cpu_class; CPUARMState *env; - uint32_t id; static int inited = 0; - id = cpu_arm_find_by_name(cpu_model); - if (id == 0) + /* One legacy alias to check */ + if (strcmp(cpu_model, "pxa270") == 0) { + cpu_model = "pxa270-a0"; + } + + klass = object_class_by_name(cpu_model); + if (klass == NULL) { return NULL; + } + cpu_class = ARM_CPU_CLASS(klass); env = g_malloc0(sizeof(CPUARMState)); cpu_exec_init(env); if (tcg_enabled() && !inited) { @@ -415,7 +422,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model) } env->cpu_model_str = cpu_model; - env->cp15.c0_cpuid = id; + env->cp15.c0_cpuid = cpu_class->cp15.c0_cpuid; cpu_reset(env); if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, @@ -431,66 +438,28 @@ CPUARMState *cpu_arm_init(const char *cpu_model) return env; } -struct arm_cpu_t { - uint32_t id; - const char *name; +struct ARMCPUListState { + fprintf_function cpu_fprintf; + FILE *file; }; -static const struct arm_cpu_t arm_cpu_names[] = { - { ARM_CPUID_ARM926, "arm926"}, - { ARM_CPUID_ARM946, "arm946"}, - { ARM_CPUID_ARM1026, "arm1026"}, - { ARM_CPUID_ARM1136, "arm1136"}, - { ARM_CPUID_ARM1136_R2, "arm1136-r2"}, - { ARM_CPUID_ARM1176, "arm1176"}, - { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, - { ARM_CPUID_CORTEXM3, "cortex-m3"}, - { ARM_CPUID_CORTEXA8, "cortex-a8"}, - { ARM_CPUID_CORTEXA9, "cortex-a9"}, - { ARM_CPUID_CORTEXA15, "cortex-a15" }, - { ARM_CPUID_TI925T, "ti925t" }, - { ARM_CPUID_PXA250, "pxa250" }, - { ARM_CPUID_SA1100, "sa1100" }, - { ARM_CPUID_SA1110, "sa1110" }, - { ARM_CPUID_PXA255, "pxa255" }, - { ARM_CPUID_PXA260, "pxa260" }, - { ARM_CPUID_PXA261, "pxa261" }, - { ARM_CPUID_PXA262, "pxa262" }, - { ARM_CPUID_PXA270, "pxa270" }, - { ARM_CPUID_PXA270_A0, "pxa270-a0" }, - { ARM_CPUID_PXA270_A1, "pxa270-a1" }, - { ARM_CPUID_PXA270_B0, "pxa270-b0" }, - { ARM_CPUID_PXA270_B1, "pxa270-b1" }, - { ARM_CPUID_PXA270_C0, "pxa270-c0" }, - { ARM_CPUID_PXA270_C5, "pxa270-c5" }, - { ARM_CPUID_ANY, "any"}, - { 0, NULL} -}; - -void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) +static void arm_cpu_list_entry(ObjectClass *klass, void *opaque) { - int i; + struct ARMCPUListState *s = opaque; - (*cpu_fprintf)(f, "Available CPUs:\n"); - for (i = 0; arm_cpu_names[i].name; i++) { - (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name); - } + (*s->cpu_fprintf)(s->file, " %s\n", + object_class_get_name(klass)); } -/* return 0 if not found */ -static uint32_t cpu_arm_find_by_name(const char *name) +void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) { - int i; - uint32_t id; + struct ARMCPUListState s = { + .cpu_fprintf = cpu_fprintf, + .file = f, + }; - id = 0; - for (i = 0; arm_cpu_names[i].name; i++) { - if (strcmp(name, arm_cpu_names[i].name) == 0) { - id = arm_cpu_names[i].id; - break; - } - } - return id; + (*cpu_fprintf)(f, "Available CPUs:\n"); + object_class_foreach(arm_cpu_list_entry, TYPE_CPU, false, &s); } void cpu_arm_close(CPUARMState *env) -- 1.7.7
