RE: [PATCH v4 27/48] igb: Clear EICR bits for delayed MSI-X interrupts

[Sriram Yagnaraman]

> -----Original Message-----
> From: Akihiko Odaki <akihiko.od...@daynix.com>
> Sent: Wednesday, 26 April 2023 12:37
> Cc: Sriram Yagnaraman <sriram.yagnara...@est.tech>; Jason Wang
> <jasow...@redhat.com>; Dmitry Fleytman <dmitry.fleyt...@gmail.com>;
> Michael S . Tsirkin <m...@redhat.com>; Alex Bennée
> <alex.ben...@linaro.org>; Philippe Mathieu-Daudé <phi...@linaro.org>;
> Thomas Huth <th...@redhat.com>; Wainer dos Santos Moschetta
> <waine...@redhat.com>; Beraldo Leal <bl...@redhat.com>; Cleber Rosa
> <cr...@redhat.com>; Laurent Vivier <lviv...@redhat.com>; Paolo Bonzini
> <pbonz...@redhat.com>; qemu-devel@nongnu.org; Tomasz Dzieciol
> <t.dziec...@partner.samsung.com>; Akihiko Odaki
> <akihiko.od...@daynix.com>
> Subject: [PATCH v4 27/48] igb: Clear EICR bits for delayed MSI-X interrupts
> 
> Section 7.3.4.1 says:
> > When auto-clear is enabled for an interrupt cause, the EICR bit is set
> > when a cause event mapped to this vector occurs. When the EITR Counter
> > reaches zero, the MSI-X message is sent on PCIe. Then the EICR bit is
> > cleared and enabled to be set by a new cause event
> 
> Signed-off-by: Akihiko Odaki <akihiko.od...@daynix.com>
> ---
>  hw/net/igb_core.c | 21 ++++++++++++---------
>  1 file changed, 12 insertions(+), 9 deletions(-)
> 
Reviewed-by: Sriram Yagnaraman <sriram.yagnara...@est.tech>