> -----Original Message-----
> From: Akihiko Odaki <akihiko.od...@daynix.com>
> Sent: Wednesday, 26 April 2023 12:37
> Cc: Sriram Yagnaraman <sriram.yagnara...@est.tech>; Jason Wang
> <jasow...@redhat.com>; Dmitry Fleytman <dmitry.fleyt...@gmail.com>;
> Michael S . Tsirkin <m...@redhat.com>; Alex Bennée
> <alex.ben...@linaro.org>; Philippe Mathieu-Daudé <phi...@linaro.org>;
> Thomas Huth <th...@redhat.com>; Wainer dos Santos Moschetta
> <waine...@redhat.com>; Beraldo Leal <bl...@redhat.com>; Cleber Rosa
> <cr...@redhat.com>; Laurent Vivier <lviv...@redhat.com>; Paolo Bonzini
> <pbonz...@redhat.com>; qemu-devel@nongnu.org; Tomasz Dzieciol
> <t.dziec...@partner.samsung.com>; Akihiko Odaki
> <akihiko.od...@daynix.com>
> Subject: [PATCH v4 45/48] igb: Clear-on-read ICR when ICR.INTA is set
>
> For GPIE.NSICR, Section 7.3.2.1.2 says:
> > ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> > clear on read occurs only if no bit is set in the IMS or at least one
> > bit is set in the IMS and there is a true interrupt as reflected in
> > ICR.INTA.
>
> e1000e does similar though it checks for CTRL_EXT.IAME, which does not exist
> on igb.
>
> Suggested-by: Sriram Yagnaraman <sriram.yagnara...@est.tech>
> Signed-off-by: Akihiko Odaki <akihiko.od...@daynix.com>
> ---
> hw/net/igb_core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index
> b68e24c9ee..29190054c6 100644
> --- a/hw/net/igb_core.c
> +++ b/hw/net/igb_core.c
> @@ -2598,6 +2598,8 @@ igb_mac_icr_read(IGBCore *core, int index)
> } else if (core->mac[IMS] == 0) {
> trace_e1000e_irq_icr_clear_zero_ims();
> igb_lower_interrupts(core, ICR, 0xffffffff);
> + } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) {
> + igb_lower_interrupts(core, ICR, 0xffffffff);
> } else if (!msix_enabled(core->owner)) {
> trace_e1000e_irq_icr_clear_nonmsix_icr_read();
> igb_lower_interrupts(core, ICR, 0xffffffff);
> --
> 2.40.0
Reviewed-by: Sriram Yagnaraman <sriram.yagnara...@est.tech>
