On 02/01/2012 08:21 PM, Peter Maydell wrote:
On 30 January 2012 07:38, Evgeny Voevodin<e.voevo...@samsung.com> wrote:
From: Maksim Kozlov<m.koz...@samsung.com>
Patch adds basic model for Exynos4210 SoC PMU.
This model implements PMU registers just as a bulk of memory. Currently,
the only reason this device exists is that secondary CPU boot loader
uses PMU INFORM5 register as a holding pen.
Your cover letter's changelog says
- hw/exynos4210_pmu.c: we do not waste space for non-existing registers
in PMU state anymore; non-existing registers are now RAZ/WI;
...wrong version of this patch, or is the cover letter wrong?
-- PMM
Cover letter is not wrong, when we send PMU patch for the first time (in
V9 series), PMU memory was modelled as continious array of registers
0x3d0c bytes long, with every register being "read as written". This was
wrong since PMU address space consists of only a handful of registers
with big empty gaps between them. Starting from V10, PMU state includes
only actually existing registers, and empty gaps between these registers
behave as RAZ/WI.
--
Mitsyanko Igor
ASWG, Moscow R&D center, Samsung Electronics
email: i.mitsya...@samsung.com
