From: Stefan Weil <s...@weilnetz.de> Signed-off-by: Stefan Weil <s...@weilnetz.de> Message-Id: <20230409201828.1159568-1...@weilnetz.de> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Acked-by: Jonathan Cameron <jonathan.came...@huawei.com> Signed-off-by: Thomas Huth <th...@redhat.com> --- docs/system/devices/cxl.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..4c38223069 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -111,7 +111,7 @@ Interfaces provided include: CXL Root Ports (CXL RP) ~~~~~~~~~~~~~~~~~~~~~~~ -A CXL Root Port servers te same purpose as a PCIe Root Port. +A CXL Root Port serves the same purpose as a PCIe Root Port. There are a number of CXL specific Designated Vendor Specific Extended Capabilities (DVSEC) in PCIe Configuration Space and associated component register access via PCI bars. -- 2.31.1
