On Thu, 2023-04-06 at 02:40 -0400, Yang Zhong wrote:
> The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> SGX enclave only supported SSE and x87 feature(xfrm=0x3).
I don't particularly like the sentence's second half, and looks it's better to
also call out "wrong XFRM value in SGX CPUID leaf" in the patch title.
Anyway ...
>
> Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
>
> Signed-off-by: Yang Zhong <yang.zh...@linux.intel.com>
> Reviewed-by: Yang Weijiang <weijiang.y...@intel.com>
...
Reviewed-by: Kai Huang <kai.hu...@intel.com>
> ---
> target/i386/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 6576287e5b..f083ff4335 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -5718,8 +5718,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
> uint32_t count,
> } else {
> *eax &= env->features[FEAT_SGX_12_1_EAX];
> *ebx &= 0; /* ebx reserve */
> - *ecx &= env->features[FEAT_XSAVE_XSS_LO];
> - *edx &= env->features[FEAT_XSAVE_XSS_HI];
> + *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
> + *edx &= env->features[FEAT_XSAVE_XCR0_HI];
>
> /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
> *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
