Ping to the Xilinx folks, do you want to review this? thanks -- PMM
On Thu, 23 Mar 2023 at 18:28, Chris Rauer <cra...@google.com> wrote: > > The problem is that the Linux driver expects the master transaction inhibit > bit(R_SPICR_MTI) to be set during driver initialization so that it can > detect the fifo size but QEMU defaults it to zero out of reset. The > datasheet indicates this bit is active on reset. > > See page 25, SPI Control Register section: > https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf > > Signed-off-by: Chris Rauer <cra...@google.com> > --- > hw/ssi/xilinx_spi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c > index 552927622f..d4de2e7aab 100644 > --- a/hw/ssi/xilinx_spi.c > +++ b/hw/ssi/xilinx_spi.c > @@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s) > txfifo_reset(s); > > s->regs[R_SPISSR] = ~0; > + s->regs[R_SPICR] = R_SPICR_MTI; > xlx_spi_update_irq(s); > xlx_spi_update_cs(s); > } > -- > 2.40.0.348.gf938b09366-goog >
