> > The only reason this doesn't have any visible effect is: > > (1) x86 doesn't have split icache/dcache so no incoherency issues > > > > I think intel new architecture does split instruction cache/data cache. > http://upload.wikimedia.org/wikipedia/commons/6/64/Intel_Nehalem_arch.svg > > But I do not know what kind of inconsistency you refer to if the icache and > dcache are split. can you please give an example.
What Peter said is that the data in icache/dcache will be sync'ed automatically on x86. What binary translation does is writing some data (which will be executed as instruction latter on) into the memory. In this case, icache/dcache should be sync'ed. Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj
