[PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set

[Daniel Henrique Barboza]

This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.

Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
---
 target/riscv/cpu.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 49f0fd2c11..7a5d202069 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1045,15 +1045,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
*cpu, Error **errp)
         cpu->cfg.ext_ifencei = true;
     }
 
-    if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
-        error_setg(errp,
-                   "I and E extensions are incompatible");
+    /* We do not have RV32E support  */
+    if (cpu->cfg.ext_e) {
+        error_setg(errp, "E extension (RV32E) is not supported");
         return;
     }
 
-    if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
-        error_setg(errp,
-                   "Either I or E extension must be set");
+    /* When RV32E is supported we'll need to check for either I or E */
+    if (!cpu->cfg.ext_i) {
+        error_setg(errp, "I extension must be set");
         return;
     }
 
-- 
2.39.2