On Thu, Feb 16, 2023 at 2:58 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > At this moment, and apparently since ever, we have no way of enabling > RISCV_FEATURE_MISA. This means that all the code from write_misa(), all > the nuts and bolts that handles how to properly write this CSR, has > always been a no-op as well because write_misa() will always exit > earlier. > > This seems to be benign in the majority of cases. Booting an Ubuntu > 'virt' guest and logging all the calls to 'write_misa' shows that no > writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling > RISC-V extensions after the machine is powered on, seems to be a niche > use. > > Regardless, the spec says that MISA is a WARL read-write CSR, and gating > the writes in the register doesn't make sense. OS and applications > should be wary of the consequences when writing it, but the write itself > must always be allowed. > > Remove the RISCV_FEATURE_MISA verification at the start of write_misa(), > removing RISCV_FEATURE_MISA altogether since there will be no more > callers of this enum. > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > --- > target/riscv/cpu.h | 1 - > target/riscv/csr.c | 5 ----- > 2 files changed, 6 deletions(-) >
Reviewed-by: Bin Meng <bm...@tinylab.org>
