Hi Mostafa,
On 2/5/23 10:43, Mostafa Saleh wrote:
> In preparation for adding stage-2 support.
> Add IDR0 fields related to stage-2.
>
> VMID16: 16-bit VMID supported.
> S2P: Stage-2 translation supported.
>
> They are described in 6.3.1 SMMU_IDR0.
>
> No functional change intended.
>
> Signed-off-by: Mostafa Saleh <smost...@google.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Eric
> ---
> hw/arm/smmuv3-internal.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
> index bce161870f..170e88c24a 100644
> --- a/hw/arm/smmuv3-internal.h
> +++ b/hw/arm/smmuv3-internal.h
> @@ -34,10 +34,12 @@ typedef enum SMMUTranslationStatus {
> /* MMIO Registers */
>
> REG32(IDR0, 0x0)
> + FIELD(IDR0, S2P, 0 , 1)
> FIELD(IDR0, S1P, 1 , 1)
> FIELD(IDR0, TTF, 2 , 2)
> FIELD(IDR0, COHACC, 4 , 1)
> FIELD(IDR0, ASID16, 12, 1)
> + FIELD(IDR0, VMID16, 18, 1)
> FIELD(IDR0, TTENDIAN, 21, 2)
> FIELD(IDR0, STALL_MODEL, 24, 2)
> FIELD(IDR0, TERM_MODEL, 26, 1)
