From: Max Chou <max.c...@sifive.com>

Signed-off-by: Max Chou <max.c...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0fa7049c3b..a4e8347d5f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1100,6 +1100,7 @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false),
     DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
     DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false),
+    DEFINE_PROP_BOOL("zvksed", RISCVCPU, cfg.ext_zvksed, false),
     DEFINE_PROP_BOOL("zvksh", RISCVCPU, cfg.ext_zvksh, false),
 
     /* Vendor-specific custom extensions */
-- 
2.39.1


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