Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <j...@jms.id.au>
---
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_gfx.h | 31 +++++++++
hw/arm/aspeed_ast2600.c | 11 ++++
hw/arm/aspeed_soc.c | 12 ++++
hw/misc/aspeed_gfx.c | 121 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 4 ++
7 files changed, 183 insertions(+)
create mode 100644 include/hw/misc/aspeed_gfx.h
create mode 100644 hw/misc/aspeed_gfx.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 8389200b2d01..7084e0efeb97 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -26,6 +26,7 @@
#include "hw/ssi/aspeed_smc.h"
#include "hw/misc/aspeed_hace.h"
#include "hw/misc/aspeed_sbc.h"
+#include "hw/misc/aspeed_gfx.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@@ -81,6 +82,7 @@ struct AspeedSoCState {
AspeedSDHCIState emmc;
AspeedLPCState lpc;
AspeedPECIState peci;
+ AspeedGFXState gfx;
SerialMM uart[ASPEED_UARTS_NUM];
Clock *sysclk;
UnimplementedDeviceState iomem;
@@ -171,6 +173,7 @@ enum {
ASPEED_DEV_EMMC,
ASPEED_DEV_KCS,
ASPEED_DEV_HACE,
+ ASPEED_DEV_GFX,
ASPEED_DEV_DPMCU,
ASPEED_DEV_DP,
ASPEED_DEV_I3C,
diff --git a/include/hw/misc/aspeed_gfx.h b/include/hw/misc/aspeed_gfx.h
new file mode 100644
index 000000000000..b0736a53f577
--- /dev/null
+++ b/include/hw/misc/aspeed_gfx.h
@@ -0,0 +1,31 @@
+/*
+ * ASPEED GFX Controller
+ *
+ * Copyright (C) 2023 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef ASPEED_GFX_H
+#define ASPEED_GFX_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_GFX "aspeed.gfx"
+#define ASPEED_GFX(obj) OBJECT_CHECK(AspeedGFXState, (obj), TYPE_ASPEED_GFX)
+
+#define ASPEED_GFX_NR_REGS (0xFC >> 2)
+
+typedef struct AspeedGFXState {
+ /* <private> */
+ SysBusDevice parent;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ uint32_t regs[ASPEED_GFX_NR_REGS];
+} AspeedGFXState;
+
+#endif /* _ASPEED_GFX_H_ */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index cd75465c2bdd..10e4a13655cc 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -43,6 +43,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_HACE] = 0x1E6D0000,
[ASPEED_DEV_SDMC] = 0x1E6E0000,
[ASPEED_DEV_SCU] = 0x1E6E2000,
+ [ASPEED_DEV_GFX] = 0x1E6E6000,
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_DP] = 0x1E6EB000,
@@ -255,6 +256,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
+ object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX);
+
object_initialize_child(obj, "iomem", &s->iomem,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "video", &s->video,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "dpmcu", &s->dpmcu,
TYPE_UNIMPLEMENTED_DEVICE);
@@ -607,6 +610,14 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
return;
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
+
+ /* GFX */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_GFX));
}
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index b05b9dd41602..053149f9ccdf 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -33,6 +33,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_SDMC] = 0x1E6E0000,
[ASPEED_DEV_SCU] = 0x1E6E2000,
[ASPEED_DEV_HACE] = 0x1E6E3000,
+ [ASPEED_DEV_GFX] = 0x1E6E6000,
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
@@ -69,6 +70,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_SDMC] = 0x1E6E0000,
[ASPEED_DEV_SCU] = 0x1E6E2000,
[ASPEED_DEV_HACE] = 0x1E6E3000,
+ [ASPEED_DEV_GFX] = 0x1E6E6000,
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
@@ -233,6 +235,8 @@ static void aspeed_soc_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
object_initialize_child(obj, "hace", &s->hace, typename);
+ object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX);
+
object_initialize_child(obj, "iomem", &s->iomem,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "video", &s->video,
TYPE_UNIMPLEMENTED_DEVICE);
}
@@ -482,6 +486,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+
+ /* GFX */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_GFX));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
diff --git a/hw/misc/aspeed_gfx.c b/hw/misc/aspeed_gfx.c
new file mode 100644
index 000000000000..42d2167b4a59
--- /dev/null
+++ b/hw/misc/aspeed_gfx.c
@@ -0,0 +1,121 @@
+/*
+ * ASPEED GFX Controller
+ *
+ * Copyright (C) 2023 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_gfx.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+
+#include "trace.h"
+
+static uint64_t aspeed_gfx_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ AspeedGFXState *s = ASPEED_GFX(opaque);
+ uint64_t val = 0;
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_GFX_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ } else {
+ val = s->regs[addr];
+ }
+
+ trace_aspeed_gfx_read(addr << 2, val);
+
+ return val;
+}
+
+static void aspeed_gfx_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedGFXState *s = ASPEED_GFX(opaque);
+
+ trace_aspeed_gfx_write(addr, data);
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_GFX_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ return;
+ }
+
+ s->regs[addr] = data;
+}
+
+static const MemoryRegionOps aspeed_gfx_ops = {
+ .read = aspeed_gfx_read,
+ .write = aspeed_gfx_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_gfx_reset(DeviceState *dev)
+{
+ struct AspeedGFXState *s = ASPEED_GFX(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void aspeed_gfx_realize(DeviceState *dev, Error **errp)
+{
+ AspeedGFXState *s = ASPEED_GFX(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gfx_ops, s,
+ TYPE_ASPEED_GFX, 0x1000);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_aspeed_gfx = {
+ .name = TYPE_ASPEED_GFX,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedGFXState, ASPEED_GFX_NR_REGS),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void aspeed_gfx_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_gfx_realize;
+ dc->reset = aspeed_gfx_reset;
+ dc->desc = "Aspeed GFX Controller";
+ dc->vmsd = &vmstate_aspeed_gfx;
+}
+
+static const TypeInfo aspeed_gfx_info = {
+ .name = TYPE_ASPEED_GFX,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedGFXState),
+ .class_init = aspeed_gfx_class_init,
+};
+
+static void aspeed_gfx_register_types(void)
+{
+ type_register_static(&aspeed_gfx_info);
+}
+
+type_init(aspeed_gfx_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 448e14b531a3..2a1f6b756fce 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -115,6 +115,7 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true:
files('pvpanic-isa.c'))
softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+ 'aspeed_gfx.c',
'aspeed_hace.c',
'aspeed_i3c.c',
'aspeed_lpc.c',
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index c47876a90262..07fccdbcc5f2 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -211,6 +211,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C
write: offset 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C
Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data)
"I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+# aspeed_gfx.c
+aspeed_gfx_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 "
data 0x%" PRIx64
+aspeed_gfx_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 "
data 0x%" PRIx64
+
# aspeed_sdmc.c
aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%"
PRIx64
aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%"
PRIx64
--
2.39.0
