Re: [PATCH 2/2] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1

[Alistair Francis]

On Fri, Dec 16, 2022 at 8:46 AM Andrew Bresticker <abres...@rivosinc.com> wrote:
>
> Per the AIA specification, writes to stimecmp from VS level should
> trap when hvictl.VTI is set since the write may cause vsip.STIP to
> become unset.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support")
> Signed-off-by: Andrew Bresticker <abres...@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 984548bf87..7d9035e7bb 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -935,6 +935,9 @@ static RISCVException write_stimecmp(CPURISCVState *env, 
> int csrno,
>      RISCVCPU *cpu = env_archcpu(env);
>
>      if (riscv_cpu_virt_enabled(env)) {
> +        if (env->hvictl & HVICTL_VTI) {
> +            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> +        }
>          return write_vstimecmp(env, csrno, val);
>      }
>
> @@ -955,6 +958,9 @@ static RISCVException write_stimecmph(CPURISCVState *env, 
> int csrno,
>      RISCVCPU *cpu = env_archcpu(env);
>
>      if (riscv_cpu_virt_enabled(env)) {
> +        if (env->hvictl & HVICTL_VTI) {
> +            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> +        }
>          return write_vstimecmph(env, csrno, val);
>      }
>
> --
> 2.25.1
>
>