Am 31. Dezember 2022 13:44:00 UTC schrieb "Philippe Mathieu-Daudé"
<phi...@linaro.org>:
>On 31/12/22 10:53, Bernhard Beschow wrote:
>>
>>
>> Am 21. November 2022 15:34:05 UTC schrieb Bernhard Beschow
>> <shen...@gmail.com>:
>>>
>>>
>>> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé"
>>> <phi...@linaro.org>:
>>>> Linux kernel expects the northbridge & southbridge chipsets
>>>> configured by the BIOS firmware. We emulate that by writing
>>>> a tiny bootloader code in write_bootloader().
>>>>
>>>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
>>>> the PIIX4 configuration space included values specific to
>>>> the Malta board.
>>>>
>>>> Set the Malta-specific IRQ routing values in the embedded
>>>> bootloader, so the next commit can remove the Malta specific
>>>> bits from the PIIX4 PCI-ISA bridge and make it generic
>>>> (matching the real hardware).
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
>>>> ---
>>>> FIXME: Missing the nanoMIPS counter-part!
>>>
>>> Who will be taking care of this? I have absolutely no clue how the
>>> write_bootloader functions work, so I don't see how to fix it.
>>
>> Ping
>
>This comment has been taken care of:
>https://lore.kernel.org/qemu-devel/a3c3f639-dbb1-88a7-43fe-547a234c5...@linaro.org/
Ah, now I see where this is going.
>However while testing the MIPS pull request I prepared I
>found a bug in the GT64120 which I'm trying to fix since
>various days... Unfortunately your series depends on it,
>so this is a blocking issue. Sorry for this long delay...
Don't worry.
How can the bug be reproduced? Is there a test run in the CI? Note that I get a
404 when trying to access
https://gitlab.com/philmd/qemu/-/commits/mips-testing/ .
Best regards,
Bernhard
>
>Phil.
